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SHF: Small: Development of Differentiable Memory Augmented Neural CPU Architecture for Cognitive Computing

SHF：小型：用于认知计算的可微内存增强神经 CPU 架构的开发

基本信息

批准号：
2008906
负责人：
Jie Gu
金额：
$ 50万
依托单位：
Northwestern University
依托单位国家：
美国
项目类别：
Standard Grant
财政年份：
2020
资助国家：
美国
起止时间：
2020-10-01 至 2024-09-30
项目状态：
已结题

来源：
https://www.nsf.gov/awardsearch/showAward?AWD_ID=2008906&HistoricalAwards=false
关键词：
SHF Small Development Differentiable Memory

项目摘要

The past half-decade has seen unprecedented growth in machine learning with deep neural networks (DNNs), which now represent the state-of-the-art in many AI applications. However, existing DNN models require substantial memory and computing power, which greatly limit their use in resource-constrained systems such as mobile and IoT devices. This project will develop new algorithms and hardware to significantly improve the efficiency of DNNs, and represents an important step towards enabling fast and adaptive DNN executions even in resource-limited environments. In that sense, this project has the potential to enable a wider deployment of machine learning, which will play a critical role in many aspects of the future smart society. The research project will provide research training opportunities to the students as well as new curriculum development by leveraging existing resources at Cornell, e.g., summer camps as well as an outreach programs for high-school students including women.This project aims to significantly improve the efficiency of DNNs while maintaining high accuracy, by co-developing algorithm optimizations and efficient hardware accelerator architecture. While there exist many lines of work on reducing DNN execution costs, the majority of these techniques are designed primarily to improve inference, and perform static optimizations that reduce computation uniformly for all inputs or only exploit a limited form of dynamic sparsity, namely zeros. This project aims to enable new performance-accuracy trade-off points for DNNs that are not possible today by exploiting general forms of dynamic sparsity that are specific to each input at run-time. More specifically, the project plans to investigate input-specific gating techniques that can remove redundant computations for both training and inference, develop dynamic quantization techniques that do not require training data, and design an efficient and unified hardware accelerator architecture that provides both real-world performance and energy improvements.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

过去五年，深度神经网络 (DNN) 的机器学习取得了前所未有的发展，目前代表了许多人工智能应用的最先进水平。然而，现有的 DNN 模型需要大量的内存和计算能力，这极大地限制了它们在移动和物联网设备等资源受限系统中的使用。该项目将开发新的算法和硬件，以显着提高 DNN 的效率，并且代表着即使在资源有限的环境中也能实现快速、自适应 DNN 执行的重要一步。从这个意义上说，该项目有潜力使机器学习得到更广泛的部署，这将在未来智能社会的许多方面发挥关键作用。该研究项目将利用康奈尔大学的现有资源，例如夏令营以及针对包括女性在内的高中生的推广计划，为学生提供研究培训机会以及新课程开发。该项目旨在通过共同开发算法优化和高效的硬件加速器架构，在保持高精度的同时显着提高DNN的效率。虽然存在许多降低 DNN 执行成本的工作，但这些技术中的大多数主要旨在改进推理，并执行静态优化，以统一减少所有输入的计算或仅利用有限形式的动态稀疏性，即零。该项目旨在通过利用运行时每个输入特定的动态稀疏性的一般形式，为 DNN 实现新的性能与准确性权衡点，而这在今天是不可能实现的。更具体地说，该项目计划研究特定于输入的门控技术，该技术可以消除训练和推理的冗余计算，开发不需要训练数据的动态量化技术，并设计一个高效且统一的硬件加速器架构，提供现实世界的性能和能源改进。该奖项反映了 NSF 的法定使命，并通过使用基金会的智力价值和更广泛的影响审查进行评估，被认为值得支持。标准。

项目成果

期刊论文数量（4）

专著数量（0）

科研奖励数量（0）

会议论文数量（0）

专利数量（0）

A General-Purpose Compute-in-Memory Processor Combining CPU and Deep Learning with Elevated CPU Efficiency and Enhanced Data Locality

结合 CPU 和深度学习的通用内存计算处理器，具有更高的 CPU 效率和增强的数据局部性

DOI：
10.23919/vlsitechnologyandcir57934.2023.10185311
发表时间：
2023
期刊：
Symposium on VLSI Technology and Circuits
影响因子：
0
作者：
Ju, Yuhao;Wei, Yijie;Chen, Xi;Gu, Jie
通讯作者：
Gu, Jie

A 65nm Systolic Neural CPU Processor for Combined Deep Learning and General-Purpose Computing with 95% PE Utilization, High Data Locality and Enhanced End-to-End Performance

A%2065nm%20Systolic%20Neural%20CPU%20Processor%20for%20Combined%20Deep%20Learning%20and%20General-Purpose%20Computing%20with%2095%%20PE%20Utilization,%20High%20Data%20Locality%20and%20Enhanced%20End-