CAREER: Scaling-up Resistive Synaptic Arrays for Neuro-inspired Computing

受神经启发的深度学习算法已经证明了它们在执行图像和语音识别等智能任务方面的能力。然而，这种深度神经网络的训练需要大量的计算资源，这对于移动的应用来说是负担不起的。深度学习的硬件加速，在速度和能效上有数量级的提高，对于基于硅CMOS技术和冯·诺依曼架构的传统硬件来说仍然是一个巨大的挑战。由于学习算法广泛地涉及矩阵运算，因此利用神经元节点中的分布式计算和突触网络中的局部存储的神经启发架构非常有吸引力。该项目的最终目标是利用新兴的纳米器件技术将神经启发的计算推向自学习芯片。实时学习和低功耗的芯片可以放置在前端传感器上，为当前的许多应用带来广泛的好处。PI将通过学生实习和技术转让与行业建立密切合作。研究与教育一体化计划将培养具有跨学科技能的学生。该项目的跨层性质涵盖了半导体器件、电路设计、电子设计自动化和机器学习，预计将为这一教育目标提供理想的平台。该项目的技术目标是克服阻碍神经启发架构的交叉阵列尺寸扩大的挑战。具有连续多级状态的电阻器件已经被提出用作交叉结构中的突触权重。然而，随着阵列尺寸的增加，与器件良率、器件可变性和阵列寄生效应相关的问题将出现，并且可能降低系统性能。PI计划通过利用设备，电路和架构的分层研究工作来应对这些挑战。研究成果包括器件紧凑模型，电路级基准模拟器，用于估计交叉阵列宏的面积/延迟/功率，以及用于有效地将学习算法映射到交叉结构中的架构工具。 PI通过与学术合作伙伴的合作，建立了一个定制的制造渠道，用于在CMOS外围电路上流片电阻器件。具有测量数据的原型芯片预计将对该领域产生重大影响，该领域以前依赖于模拟来预测大规模阵列性能。

Neuro-inspired deep learning algorithms have demonstrated their power in executing intelligent tasks such as image and speech recognition. However, training of such deep neural networks requires huge amount of computational resources that are not affordable for mobile applications. Hardware acceleration of deep learning, with orders of magnitude improvement in speed and energy efficiency, remains a grand challenge for the conventional hardware based on silicon CMOS technology and von-Neumann architecture. As the learning algorithms extensively involve matrix operations, neuro-inspired architectures that leverage the distributed computing in the neuron nodes and localized storage in the synaptic networks are very attractive. The ultimate goal of this project is to advance the neuro-inspired computing with emerging nano-device technologies towards a self-learning chip. A chip that learns in real-time and consumes low-power can be placed at frontend sensors, bringing broad benefits for a number of current applications. The PI will establish close collaboration with industry through student internships and technology transfer. The plan for integration of research and education will train students with interdisciplinary skills. The cross-layer nature of this project ranging from semiconductor device, circuit design, electronic design automation, and machine learning is expected to provide an ideal platform for this educational goal.The technical goal of this project is to overcome the challenges that prevent scaling up of the crossbar array size for neuro-inspired architecture. Resistive devices with continuous multilevel states have been proposed to function as synaptic weights in the crossbar architecture. However, with the increase of the array size, issues associated with device yield, device variability, and array parasitics will arise and may degrade the system performance. The PI plans to tackle these challenges by exploiting hierarchical research efforts from devices, circuits and architectures. The outcome of the research includes device compact model, circuit-level benchmark simulator for estimating the area/latency/power of the crossbar array macro, and architectural tool for efficiently mapping the learning algorithms into the crossbar architecture. The PI has established a custom fabrication channel for tape-out of resistive devices on top of CMOS peripheral circuits via his collaboration with academic partners. The prototype chip with measured data is expected to make a strong impact on this field, which previously relied on the simulations for predicting large-scale array performance.