EAGER: Monolithic 3D Integration of Resistive Random Access Memory (ReRAM): A Technological Exploration

点击翻译按钮获取中文摘要

With the rapid growth of big data, next generation non-volatile memory technologies are needed to enable a large capacity and fast bandwidth. The resistive random access memory (ReRAM) technology is one of the emerging candidates beyond the scaling limit of today's FLASH technology. The research and development of the ReRAM technology will benefit nearly every digital device available today from consumer electronics to enterprise electronics. It may also spawn new applications involving the computation on the exascale of data, e.g. data mining, machine learning, and bio-informatics etc. thus benefitting the semiconductor industry at large. Student summer internships are planned with the industrial partners, which will be invaluable for broadening the knowledge and skills of the students. The tools and techniques developed in this research will be used in the newly developed seminar course on memory design at ASU. The PI will make simulator tools available for use by other educators, researchers, and industry practitioners. Dissemination of research findings will also be carried out through conference tutorials, panel discussions, and workshops. A concerted effort will be made to involve underrepresented groups and undergraduate students in this research, and also to promote the K-12 students to major in science and engineering. This proposal aims to tackle the fundamental technological challenges for the monolithic 3D integration of ReRAM. Although the ReRAM technology shows very attractive characteristics at single cell level, at the array level its lower integration density limits its economical competiveness over the mainstream NAND FLASH technology. The project examines the use of monolithic 3D integration of ReRAM as a promising approach for enabling ultra-high density cross-point memory architecture. The proposed research activities focus on the device-level engineering with the design targets from the circuit-level array modeling, aiming at enabling the large-scale integration of 3D ReRAM technology. Array macro model that can assess integration density, cost per bit, read/write margin, access latency, and power/energy consumption will be developed and calibrated by SPICE simulation. Device prototypes for 3D ReRAM will be fabricated and optimized towards the desired targets given by the array macro model. All device engineering activities will leverage the existing knowledge of the electrode/oxide interface engineering and oxide/oxide interface engineering and further contribute to new understandings of relevant issues.