CAREER: Scaling-up Resistive Synaptic Arrays for Neuro-inspired Computing

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Neuro-inspired deep learning algorithms have demonstrated their power in executing intelligent tasks such as image and speech recognition. However, training of such deep neural networks requires huge amount of computational resources that are not affordable for mobile applications. Hardware acceleration of deep learning, with orders of magnitude improvement in speed and energy efficiency, remains a grand challenge for the conventional hardware based on silicon CMOS technology and von-Neumann architecture. As the learning algorithms extensively involve matrix operations, neuro-inspired architectures that leverage the distributed computing in the neuron nodes and localized storage in the synaptic networks are very attractive. The ultimate goal of this project is to advance the neuro-inspired computing with emerging nano-device technologies towards a self-learning chip. A chip that learns in real-time and consumes low-power can be placed at frontend sensors, bringing broad benefits for a number of current applications. The PI will establish close collaboration with industry through student internships and technology transfer. The plan for integration of research and education will train students with interdisciplinary skills. The cross-layer nature of this project ranging from semiconductor device, circuit design, electronic design automation, and machine learning is expected to provide an ideal platform for this educational goal.The technical goal of this project is to overcome the challenges that prevent scaling up of the crossbar array size for neuro-inspired architecture. Resistive devices with continuous multilevel states have been proposed to function as synaptic weights in the crossbar architecture. However, with the increase of the array size, issues associated with device yield, device variability, and array parasitics will arise and may degrade the system performance. The PI plans to tackle these challenges by exploiting hierarchical research efforts from devices, circuits and architectures. The outcome of the research includes device compact model, circuit-level benchmark simulator for estimating the area/latency/power of the crossbar array macro, and architectural tool for efficiently mapping the learning algorithms into the crossbar architecture. The PI has established a custom fabrication channel for tape-out of resistive devices on top of CMOS peripheral circuits via his collaboration with academic partners. The prototype chip with measured data is expected to make a strong impact on this field, which previously relied on the simulations for predicting large-scale array performance.