Low Temperature Embedded Memory Devices for Near-Memory and In-Memory Computing

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High performance computing in data centers enables numerous commercial and critical military applications, including genomic sequencing, computational chemistry, financial risk modeling, weather prediction, complex system design, multi-domain physical simulations, crypto-analysis, and deep learning, etc. Historically, improvements in high-performance computing have been driven by new integrated-circuit technology scaling following Moore’s law. That paradigm is no longer bringing significant advances in the last decade due to the difficulty in continuing conventional transistor scaling, particularly with respect to power reduction. While logic circuitry is typically designed to operate at room temperature, it is well known that transistor characteristics can improve significantly at lower temperatures. If cryogenic computing is successful at 77 Kelvin (the liquid-nitrogen temperature), the energy savings for data centers could potentially overwhelm the cooling power cost, resulting in the reduction of carbon footprint for society. Most prior research have been focused on low-temperature logic transistors (including cache memory) and compute-intensive microprocessor design. On the contrary, low-temperature memory devices and data-intensive accelerator design that employs near-memory and in-memory compute paradigms are much less explored. This award will also train the next generation of students as the workforce for revamping the US domestic semiconductors and microelectronics. This award will undertake a comprehensive characterization of embedded-memory devices fabricated in-house and test vehicles with collaborative foundry partners. The embedded-memory devices of interests here include resistive random-access memory (RRAM) and ferroelectric field-effect transistors (FeFET) that offer multilevel states for the read-intensive weight memories, and 2-transistor gain-cell-based embedded dynamic random access memory (eDRAM) for write-intensive buffer memories. The goal of this project is technology pathfinding to enable 10× energy saving and 3× performance improvement (in terms of throughput or latency) for data-intensive workloads (e.g., machine/deep learning) at 77 K when compared to room temperature. The outcome of this award includes not only a collection of first-hand experimental data of embedded memories at cryogenic temperatures but also a benchmark framework for design-technology co-optimization of near-memory and in-memory compute accelerators at cryogenic temperatures.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.