CRII: SHF: System-Level Detection, Modeling, and Mitigation of DRAM Failures to Enable Efficient Scaling of DRAM Memory

未来的计算系统将以海量数据处理为主导。这些系统将不得不计算来自无处不在的网络和物联网（例如传感器、自动驾驶汽车、移动设备、社交媒体）的以用户为中心的指数级增长的数据。与此同时，科学创新的前进将在很大程度上依赖于对科学实验产生的大容量数据集（分析引力波、粒子加速器中的粒子碰撞等）的快速高效计算。然而，当前的计算系统受到内存的瓶颈，但高容量、可扩展的内存对于未来快速高效的数据处理至关重要。不幸的是，主要的内存底层技术DRAM正面临着重大的扩展挑战。随着DRAM缩小到更小的技术节点，单元变得更脆弱，导致DRAM故障。在不牺牲可靠性的情况下实现更高容量的存储系统是主要的研究挑战。本研究的重点是开发能够为未来系统实现可扩展存储系统的基础突破。该提案提供了研究计划和思路，通过将提供可靠的DRAM操作的责任与设计具有较小特征尺寸的存储单元的责任分离开来，以一种全新的方法解决DRAM缩放挑战。本提案的核心愿景是开发系统级检测和缓解DRAM故障的技术，以便可以在不提供任何可靠性保证的情况下制造更小的单元。预计本研究中开发的想法将弥合电路和系统之间的差距，并将实现解决DRAM缩放挑战的整体方法。工作的横切性质将影响电路级测试、计算机体系结构、操作系统和系统设计，并且可以潜在地实现不同社区（测试和系统/体系结构）之间的协作。在这项研究中发展起来的想法不仅会影响计算机领域的创新，还会帮助许多科学领域向新的创新飞跃。这项研究的结果将纳入现有的和新的课程，以影响学生的培训和教育，其设计重点是吸引少数群体学习硬件和系统设计，以加强该领域的多样性。

Future computing systems will be dominated by enormous amount of data processing. These systems will have to compute over exponentially growing user focused data from ubiquitous network and internet of things (e.g., sensors, self-driving cars, mobile devices, social media). At the same time, the forward progress of scientific innovations will greatly depend on the fast and efficient computation on high volume datasets generated from scientific experiments (analyzing gravitational waves, colliding particles in the particle accelerators, etc.). However, the current computing systems are bottlenecked by memory, but high capacity, scalable memory is essential for fast and efficient data processing in the future. Unfortunately, DRAM, the predominant underlying technology for memory is facing major scaling challenge. As DRAM scales down to smaller technology nodes, cells become more vulnerable, resulting in DRAM failures. Enabling a higher capacity memory system without sacrificing reliability is a major research challenge.This research focuses on developing fundamental breakthrough that can enable scalable memory system for the future systems. This proposal provides research plan and ideas to solve the DRAM scaling challenge in a completely new approach by separating the responsibility of providing reliable DRAM operation from designing memory cells with smaller feature size. The central vision of this proposal is to develop system-level detection and mitigation techniques for DRAM failures such that cells can be manufactured to be smaller without providing any reliability guarantee. It is expected that ideas developed in this research will bridge the gap between circuits and systems and will enable a holistic approach to solve the DRAM scaling challenge. The cross-cutting nature of the work will influence circuit-level testing, computer architecture, and OS and systems design and can potentially enable collaboration between different communities (testing and systems/architecture). The ideas developed in this research will not only impact innovation in computing, but will also help numerous scientific fields to take a leap towards new innovations. The results of this research will be integrated to existing and new courses to impact student training and education, designed focusing on attracting the minority groups towards hardware and systems design to enhance diversity in the field.