CRII: SHF: System-Level Detection, Modeling, and Mitigation of DRAM Failures to Enable Efficient Scaling of DRAM Memory

未来的计算系统将被大量的数据处理所主导。这些系统将不得不计算来自无处不在的网络和物联网（例如，传感器、自动驾驶汽车、移动的设备、社交媒体）。与此同时，科学创新的向前发展将在很大程度上取决于对科学实验产生的大容量数据集（分析引力波，粒子加速器中的碰撞粒子等）的快速有效计算。然而，当前的计算系统都受到存储器的限制，但是高容量、可扩展的存储器对于未来快速高效的数据处理是必不可少的。不幸的是，DRAM，用于存储器的主要基础技术正面临着重大的扩展挑战。随着DRAM缩小到更小的技术节点，单元变得更脆弱，导致DRAM故障。在不牺牲可靠性的情况下实现更高容量的存储系统是一个主要的研究挑战。本研究的重点是开发能够为未来系统提供可扩展存储系统的根本突破。该提案提供了研究计划和想法，以通过将提供可靠DRAM操作的责任与设计具有较小特征尺寸的存储器单元分离来以全新的方法解决DRAM缩放挑战。该提案的中心愿景是开发针对DRAM故障的系统级检测和缓解技术，以便可以在不提供任何可靠性保证的情况下将单元制造得更小。 预计在这项研究中开发的想法将弥合电路和系统之间的差距，并将使一个整体的方法来解决DRAM规模的挑战。这项工作的跨领域性质将影响电路级测试、计算机体系结构、操作系统和系统设计，并有可能实现不同社区（测试和系统/体系结构）之间的协作。在这项研究中开发的想法不仅会影响计算创新，而且还将帮助许多科学领域实现新的创新。这项研究的结果将被整合到现有的和新的课程，以影响学生的培训和教育，旨在吸引少数群体对硬件和系统设计，以提高该领域的多样性。

Future computing systems will be dominated by enormous amount of data processing. These systems will have to compute over exponentially growing user focused data from ubiquitous network and internet of things (e.g., sensors, self-driving cars, mobile devices, social media). At the same time, the forward progress of scientific innovations will greatly depend on the fast and efficient computation on high volume datasets generated from scientific experiments (analyzing gravitational waves, colliding particles in the particle accelerators, etc.). However, the current computing systems are bottlenecked by memory, but high capacity, scalable memory is essential for fast and efficient data processing in the future. Unfortunately, DRAM, the predominant underlying technology for memory is facing major scaling challenge. As DRAM scales down to smaller technology nodes, cells become more vulnerable, resulting in DRAM failures. Enabling a higher capacity memory system without sacrificing reliability is a major research challenge.This research focuses on developing fundamental breakthrough that can enable scalable memory system for the future systems. This proposal provides research plan and ideas to solve the DRAM scaling challenge in a completely new approach by separating the responsibility of providing reliable DRAM operation from designing memory cells with smaller feature size. The central vision of this proposal is to develop system-level detection and mitigation techniques for DRAM failures such that cells can be manufactured to be smaller without providing any reliability guarantee. It is expected that ideas developed in this research will bridge the gap between circuits and systems and will enable a holistic approach to solve the DRAM scaling challenge. The cross-cutting nature of the work will influence circuit-level testing, computer architecture, and OS and systems design and can potentially enable collaboration between different communities (testing and systems/architecture). The ideas developed in this research will not only impact innovation in computing, but will also help numerous scientific fields to take a leap towards new innovations. The results of this research will be integrated to existing and new courses to impact student training and education, designed focusing on attracting the minority groups towards hardware and systems design to enhance diversity in the field.