SaTC: STARSS: Small: Collaborative: Managing Hardware Security in Three-Dimensional Integrated Circuits

SaTC:STARSS:小型:协作:管理三维集成电路中的硬件安全

基本信息

  • 批准号:
    1717130
  • 负责人:
  • 金额:
    $ 15.67万
  • 依托单位:
  • 依托单位国家:
    美国
  • 项目类别:
    Standard Grant
  • 财政年份:
    2017
  • 资助国家:
    美国
  • 起止时间:
    2017-10-01 至 2021-09-30
  • 项目状态:
    已结题

项目摘要

Vertically stacked three-dimensional (3D) integration of semiconductor chips is an emerging technology to ensure continued growth in transistor density and performance of integrated circuits (ICs). Despite the well-characterized advantages and limitations, the hardware security of such circuits has not received much attention. With shrinking number of trusted circuit manufacturers, trustworthiness of electronic devices is a growing concern. Vertical integration brings unexplored and unique challenges in managing hardware security. This research develops a cross-layer framework to manage and guarantee hardware security in 3D ICs. The systematic framework developed by this research assesses and enhances trustworthiness of 3D ICs for both commercial and defense-specific applications. Proposed project also supports diverse educational and outreach programs with emphasis on underrepresented groups in both New Hampshire and Stony Brook, Long Island. Existing hardware security solutions are for 2D ICs manufactured by a trusted foundry. Unfortunately, new security problems arise when multiple dies from different vendors are stacked in a 3D IC. Proposed research targets these security weaknesses with an emphasis on the trustworthiness of vertical communications. Solution mechanisms to prevent attacks on the vertical communication path will be investigated to achieve secure die-to-die communication. A secure power delivery architecture will be designed to detect small hardware Trojans in any die within the stack. A switching noise analysis based scheme will be investigated to detect malicious behavior in vertical communication paths.
半导体芯片的垂直堆叠三维(3D)集成是确保集成电路(IC)的晶体管密度和性能持续增长的新兴技术。尽管这些电路具有很好的优点和局限性,但其硬件安全性并未受到太多关注。随着可信电路制造商数量的减少,电子设备的可信度日益受到关注。垂直整合在管理硬件安全性方面带来了前所未有的独特挑战。本研究发展一个跨层架构来管理和保障3D IC的硬件安全。本研究开发的系统框架评估并增强了3D IC在商业和国防特定应用中的可信度。拟议的项目还支持多样化的教育和推广方案,重点是新罕布什尔州和长岛斯托尼布鲁克的代表性不足的群体。现有的硬件安全解决方案适用于由值得信赖的代工厂制造的2D IC。不幸的是,当来自不同供应商的多个管芯堆叠在3D IC中时,会出现新的安全问题。拟议的研究针对这些安全弱点,重点是垂直通信的可信度。将研究防止对垂直通信路径的攻击的解决方案机制,以实现安全的管芯到管芯通信。将设计一个安全的电力输送架构,以检测堆栈内任何芯片中的小型硬件木马。一个基于开关噪声分析的方案将被调查,以检测垂直通信路径中的恶意行为。

项目成果

期刊论文数量(8)
专著数量(0)
科研奖励数量(0)
会议论文数量(0)
专利数量(0)
Invariance Checking based Trojan Detection Method for Three-Dimensional Integrated Circuits
基于不变性检验的三维集成电路木马检测方法
Towards Enhancing Power-Analysis Attack Resilience for Logic Locking Techniques
增强逻辑锁定技术的功率分析攻击弹性
FTAI: Frequency-based Trojan-Activity Identification Method for 3D Integrated Circuits
FTAI:基于频率的 3D 集成电路木马活动识别方法
Assessing Correlation Power Analysis (CPA) Attack Resilience of Transistor-Level Logic Locking
Emerging Applications of 3D Integration and Approximate Computing in High-Performance Computing Systems: Unique Security Vulnerabilities
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Qiaoyan Yu其他文献

Attack-Resilient Temperature Sensor Design
抗攻击温度传感器设计
Fault-tolerant methods for a new lightweight cipher SIMON
新型轻量级密码SIMON的容错方法
A New Analytical Model of SET Latching Probability for Circuits Experiencing Single- or Multiple-Cycle Single-Event Transients
Adaptive Error Control Coding at Datalink Layer
数据链路层的自适应错误控制编码
  • DOI:
  • 发表时间:
    2012
  • 期刊:
  • 影响因子:
    0
  • 作者:
    Qiaoyan Yu;P. Ampadu
  • 通讯作者:
    P. Ampadu
DSD: A Dynamic State-Deflection Method for Gate-Level Netlist Obfuscation
DSD:一种用于门级网表混淆的动态状态偏转方法

Qiaoyan Yu的其他文献

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{{ truncateString('Qiaoyan Yu', 18)}}的其他基金

CAREER: Proactive Defense Methods for Chip Integrity and Security
职业:芯片完整性和安全性的主动防御方法
  • 批准号:
    1652474
  • 财政年份:
    2017
  • 资助金额:
    $ 15.67万
  • 项目类别:
    Continuing Grant

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