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SaTC: STARSS: Small: Collaborative: Managing Hardware Security in Three-Dimensional Integrated Circuits

SaTC：STARSS：小型：协作：管理三维集成电路中的硬件安全

基本信息

批准号：
1717130
负责人：
Qiaoyan Yu
金额：
$ 15.67万
依托单位：
University of New Hampshire
依托单位国家：
美国
项目类别：
Standard Grant
财政年份：
2017
资助国家：
美国
起止时间：
2017-10-01 至 2021-09-30
项目状态：
已结题

来源：
https://www.nsf.gov/awardsearch/showAward?AWD_ID=1717130&HistoricalAwards=false
关键词：
SaTC STARSS Small Collaborative Managing

项目摘要

Vertically stacked three-dimensional (3D) integration of semiconductor chips is an emerging technology to ensure continued growth in transistor density and performance of integrated circuits (ICs). Despite the well-characterized advantages and limitations, the hardware security of such circuits has not received much attention. With shrinking number of trusted circuit manufacturers, trustworthiness of electronic devices is a growing concern. Vertical integration brings unexplored and unique challenges in managing hardware security. This research develops a cross-layer framework to manage and guarantee hardware security in 3D ICs. The systematic framework developed by this research assesses and enhances trustworthiness of 3D ICs for both commercial and defense-specific applications. Proposed project also supports diverse educational and outreach programs with emphasis on underrepresented groups in both New Hampshire and Stony Brook, Long Island. Existing hardware security solutions are for 2D ICs manufactured by a trusted foundry. Unfortunately, new security problems arise when multiple dies from different vendors are stacked in a 3D IC. Proposed research targets these security weaknesses with an emphasis on the trustworthiness of vertical communications. Solution mechanisms to prevent attacks on the vertical communication path will be investigated to achieve secure die-to-die communication. A secure power delivery architecture will be designed to detect small hardware Trojans in any die within the stack. A switching noise analysis based scheme will be investigated to detect malicious behavior in vertical communication paths.

半导体芯片的垂直堆叠三维（3D）集成是一项新兴技术，以确保晶体管密度和集成电路（ic）性能的持续增长。尽管具有明显的优势和局限性，但这种电路的硬件安全性并没有受到太多的关注。随着可信赖的电路制造商数量的减少，电子设备的可信赖性日益受到关注。垂直集成在管理硬件安全性方面带来了未开发的独特挑战。本研究开发了一个跨层架构来管理和保证3D集成电路的硬件安全。本研究开发的系统框架评估和增强了商业和国防特定应用的3D集成电路的可信度。拟议的项目还支持多样化的教育和推广项目，重点关注新罕布什尔州和长岛石溪的弱势群体。现有的硬件安全解决方案适用于由值得信赖的代工厂制造的2D ic。不幸的是，当来自不同供应商的多个芯片堆叠在3D IC中时，会出现新的安全问题。拟议的研究针对这些安全弱点，强调垂直通信的可信度。将研究防止垂直通信路径上攻击的解决方案机制，以实现安全的模对模通信。将设计一个安全的电力传输架构，以检测堆栈内任何芯片中的小型硬件木马。本文将研究一种基于交换噪声分析的方案来检测垂直通信路径中的恶意行为。

项目成果

期刊论文数量（8）

专著数量（0）

科研奖励数量（0）

会议论文数量（0）

专利数量（0）

Invariance Checking based Trojan Detection Method for Three-Dimensional Integrated Circuits

基于不变性检验的三维集成电路木马检测方法

DOI：
发表时间：
2020
期刊：
2020 International Symposium on Circuits and Systems
影响因子：
0
作者：
Zhang, Zhiming;Yu, Qiaoyan
通讯作者：
Yu, Qiaoyan

Towards Enhancing Power-Analysis Attack Resilience for Logic Locking Techniques

增强逻辑锁定技术的功率分析攻击弹性

DOI：
10.1109/isvlsi51109.2021.00034
发表时间：
2021
期刊：
IEEE Computer Society Annual Symposium on VLSI (ISVLSI
影响因子：
0
作者：
Zhang, Zhiming;Miketic, Ivan;Salman, Emre;Yu, Qiaoyan
通讯作者：
Yu, Qiaoyan

FTAI: Frequency-based Trojan-Activity Identification Method for 3D Integrated Circuits

FTAI：基于频率的 3D 集成电路木马活动识别方法

DOI：
10.1109/mwscas48704.2020.9184506
发表时间：
2020
期刊：
2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS
影响因子：
0
作者：
Zhang, Zhiming;Yu, Qiaoyan
通讯作者：
Yu, Qiaoyan

Assessing Correlation Power Analysis (CPA) Attack Resilience of Transistor-Level Logic Locking