EAGER: Monolithic Integration of 1000-ch Neural Interface System on a Single Silicon Die

来自感觉皮层和初级运动皮层的大量神经元群的平行记录揭示了神经信号编码的丰富信息，并指导了认知和运动行为的恢复研究。在这种设备中，信息的质量取决于被记录的神经信号的密度。目前脑机接口的记录密度仍不足以与临床相关，需要进行重大改进以帮助严重残疾患者完全恢复行动能力或其他受损功能。然而，缺乏适应电极-放大器对之间大量导线数量的技术，以及植入设备中密封包装的复杂性，在超过1000通道的临床相关方面提出了巨大的挑战。这个探索性研究（EAGER）项目将研究一种变革性的方法，通过将整个无线神经系统集成到薄硅衬底中来设计无线神经接口系统，从而为未来脑机接口研究和临床应用开发可扩展的神经接口系统引入一条途径。这项探索性研究的成功将改变脑机接口开发人员采用的设计方法，该方法涉及使用外部电线进行互连，从而使包装变得复杂，并将对专注于认知和运动行为的研究产生直接影响，这些研究需要直接从皮层提取高密度神经记录来指导神经假肢。它还将通过使用常见的半导体制造方法来制造设备，从而显著降低制造成本，这可能会为有需要的患者带来更实惠的神经义肢。全植入式神经接口系统是由许多组件组成的复杂集成系统，包括：电极阵列、放大器、处理器、无线发射器和电池。现有的每个系统都使用导线馈线在组件之间建立电气连接，并且连接用套管/包装绝缘，以防止植入过程中泄漏。这种方法存在许多局限性：可扩展性受到可用馈线数量的严重限制，运行时间受限于电池容量，金属外壳可能会阻碍无线传输，非金属包装的长期耐用性值得怀疑，并且体积庞大的植入装置使手术过程复杂化并给患者带来不适/风险。因此，需要开发具有大规模记录能力的新型脑机接口，以推进脑基础研究、大规模脑制图和脑机接口的临床翻译。这个项目的目标是在硅衬底上单片集成一个1000赫兹的神经接口系统。每个组件的单片集成到单个硅芯片中，通过消除外部电线和在集成电路中使用亚微米互连连接所有电子互连，实现高密度记录。与传统方法相比，这种方法产生了前所未有的优势，包括设计简单和消除复杂的包装。本研究包括以下工作：(1)柱状电极阵列的片上集成；(2)射频平面线圈和电容器的背板集成；(3)低功耗小占位放大器阵列和高通量神经记录外围电路的设计。

The parallel recordings from large neuron populations in the sensory cortex and primary motor cortex reveal the rich information encoded into neural signals, and guide research in restoring cognitive and motor behaviors. In such devices, the quality of information relies on the density of neural signals being recorded. The recording density in the current brain-machine interface remains insufficient to be clinically relevant and significant improvements are required to help severely disabled patients to fully regain mobility or other impaired functions. However, the lack of technology to accommodate the massive wire counts between electrode-amplifier pairs and the complexity in the hermetic packaging in implant devices present large challenges in moving forward beyond 1000 channels to be clinically relevant. This Early-concept Grant for Exploratory Research (EAGER) project will investigate a transformative approach to design a wireless neural interface system by integrating the entire wireless neural system into a thin silicon substrate, and, thus, introduce an avenue for developing a scalable neural interface system for future brain-machine interface research and clinical use. The success of this exploratory study will transform the design approach taken by brain-machine interface developers, which involves the use of external wires for interconnections and thus complicates the packaging, and will have an immediate impact in research studies focused on cognitive and motor behaviors that demands the extraction of high density neural recordings directly from the cortex to guide the neural prosthetics. It will also significantly lower the manufacturing cost by fabricating the device using common semiconductor fabrication methods, which may result in more affordable neural prosthetics for patients in need.Fully-implantable neural interface systems are designed with a complex integration of many components including: electrode arrays, amplifiers, processors, wireless transmitters, and a battery. Every existing system uses wire feedthroughs to establish electrical connections between the components, and the connections are insulated with casing/packaging to prevent leakage during implant. This method presents many limitations: the scalability is severely limited by the number of feedthroughs available, the runtime is limited to the battery capacity, the metal casing can impede wireless transmissions, the long-term durability is questionable with non-metallic packaging, and the bulky implant device complicates the surgical procedure and introduces discomfort/risks to patients. Thus, the development of a new brain-machine interface with large-scale recording capability are needed to advance basic brain research, large-scale brain mapping and clinical translations of brain-machine interface. This project aims to monolithically integrate a 1000-ch neural interface system in a silicon substrate. The monolithic integration of every component into a single silicon die enables high-density recordings by eliminating external wires and linking all the electronic interconnections using sub-micron interconnects in integrated circuits. This approach yields unprecedented advantages, compared to the conventional approach, including the design simplicity and the elimination of complex packaging. The study is composed of the following efforts: (1) On-chip integration of the pillar electrode array, (2) Backplane integration of RF planar coils and capacitors, and (3) Design of low-power small footprint amplifier array and peripheral circuitries for high-throughput neural recordings.