SHF: Small: Collaborative Research: Harvesting Wasted Time and Existing Circuitry for Efficient Field Testing

SHF：小型：协作研究：利用浪费的时间和现有电路进行高效的现场测试

• 批准号: 1812777
• 负责人: Kundan Nepal
• 金额: $ 9.35万
• 依托单位: University of St. Thomas
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2018
• 资助国家: 美国
• 起止时间: 2018-10-01 至 2022-09-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1812777&HistoricalAwards=false
• 关键词: SHF; Small; Collaborative; Research; Harvesting

Digital integrated circuits (ICs) are the "brains" in the electronic devices used throughout modern society. It is essential that these devices work correctly and reliably - especially in critical applications such as autonomous vehicles, infrastructure, the financial system, and health care. In such applications, highly effective and efficient testing should be done in the field to identify problems that may arise after the device has been sent to the customer. Thus, in this project, new ways of using circuitry already present on modern ICs while efficiently creating, applying, and transporting field-based tests to different parts of the chip will be investigated. At the same time, educational opportunities made possible through the project will be pursued, including the use of research findings in courses, the involvement of graduate and undergraduate students in the research, and outreach to high school students through summer camps and research opportunities. The inclusion of members of underrepresented groups in these educational opportunities will be a focus of the investigators, who already have a proven record in mentoring such students in research. To address the field-testing issues, three major tasks will be performed in this research. First, methods that use existing error-detection circuitry in an IC to make the field testing process more efficient will be explored. In particular, times when the IC is operating in normal functional mode will be used to test for the presence of some faults. Testing for those same faults in dedicated test sessions can then be avoided, reducing test time and the amount of time a circuit must be taken offline for test. Next, methods for effectively using otherwise wasted time during dedicated test sessions to detect faults will be explored. Finally, approaches that optimize the internal test network to efficiently send data used for test throughout a chip will be investigated. Taken together, these approaches should enable field-based test to achieve high fault coverage while minimizing test time, thus enhancing the reliability of devices that so many people depend upon every day.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

数字集成电路（IC）是现代社会使用的电子设备中的“大脑”。 这些设备必须正确可靠地工作，特别是在自动驾驶汽车、基础设施、金融系统和医疗保健等关键应用中。 在此类应用中，应在现场进行高效和高效的测试，以识别设备发送给客户后可能出现的问题。 因此，在这个项目中，将研究使用现代IC上已经存在的电路的新方法，同时有效地创建，应用和传输基于现场的测试到芯片的不同部分。与此同时，将利用通过该项目提供的教育机会，包括在课程中使用研究成果，让研究生和本科生参与研究，并通过夏令营和研究机会向高中生推广。 将代表性不足的群体的成员纳入这些教育机会将是调查人员的重点，他们在指导这些学生进行研究方面已经有了良好的记录。 为了解决现场测试问题，本研究将执行三项主要任务。 首先，将探索使用IC中现有的错误检测电路来使现场测试过程更有效的方法。 特别地，IC在正常功能模式下操作的时间将用于测试某些故障的存在。 这样就可以避免在专用测试会话中测试这些相同的故障，从而减少测试时间和电路必须离线测试的时间量。 接下来，将探索在专用测试会话期间有效利用否则浪费的时间来检测故障的方法。 最后，将研究优化内部测试网络以有效发送用于整个芯片的测试数据的方法。 综合考虑，这些方法应使现场测试达到高故障覆盖率，同时最大限度地减少测试时间，从而提高许多人每天依赖的设备的可靠性。该奖项反映了NSF的法定使命，并通过使用基金会的知识价值和更广泛的影响审查标准进行评估，被认为值得支持。

项目成果

Enhanced DFT for Fortuitous Detection of Transition Faults During Scan Shift

增强型 DFT 用于扫描移位期间转换故障的偶然检测

• DOI: 10.1109/mdts54894.2022.9826976
• 发表时间: 2022
• 期刊: 2022 IEEE 31st Microelectronics Design & Test Symposium (MDTS
• 作者: Jiang, Hui;Dworak, Jennifer;Nepal, Kundan;Manikas, Theodore
• 通讯作者: Manikas, Theodore

Low Power Shift and Capture through ATPG-Configured Embedded Enable Capture Bits

通过 ATPG 配置的嵌入式使能捕获位实现低功耗移位和捕获

• 发表时间: 2021
• 期刊: International Test Conference (ITC
• 作者: Sun, Yi;Jiang, Hui;Ramakrishnan, Lakshmi;Dworak, Jennifer;Nepal, Kundan;Manikas, Thodore;Bahar, R. Iris
• 通讯作者: Bahar, R. Iris

Repurposing FPGAs for Tester Design to Enhance Field-Testing in a 3D Stack

重新利用 FPGA 进行测试仪设计以增强 3D 堆栈中的现场测试

• DOI: 10.1007/s10836-019-05845-5
• 发表时间: 2019
• 期刊: Journal of Electronic Testing
• 作者: Sun, Yi;Zhang, Fanchen;Jiang, Hui;Nepal, Kundan;Dworak, Jennifer;Manikas, Theodore;Bahar, R. Iris
• 通讯作者: Bahar, R. Iris

Harvesting Wasted Clock Cycles for Efficient Online Testing

收集浪费的时钟周期以进行高效的在线测试

• DOI: 10.1109/ets56758.2023.10173955
• 发表时间: 2023
• 期刊: 2023 IEEE European Test Symposium
• 作者: Yassien, Eslam;Xu, Yongjia;Jiang, Hui;Nguyen, Thach;Dworak, Jennifer;Manikas, Theodore;Nepal, Kundan
• 通讯作者: Nepal, Kundan

Test Architecture for Fine Grained Capture Power Reduction

• DOI: 10.1109/icecs46596.2019.8964790
• 发表时间: 2019-11
• 期刊: 2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS)
• 作者: Yi Sun;Hui Jiang;L. Ramakrishnan;Matan Segal;Kundan Nepal;Jennifer Dworak;T. Manikas;R. I. Bahar-R.-I.