CAREER: SHF: Chiplet-Package Co-Optimizations for 2.5D Heterogeneous SoCs with Low-Overhead IOs

2.5维小芯片的设计作为一种灵活的、可扩展的摩尔比摩尔解决方案，正在变得越来越流行，以推动集成电路芯片的计算性能。通过异构集成，每个IP模块都可以使用最佳技术节点实现，从而最大限度地提高设计灵活性和性能。然而，与单片2D芯片相比的缺点是由小芯片间通信引入的大开销。与片上互连相比，封装上导线具有大得多的寄生效应。因此，它们可能会降低2.5D系统的性能和能效。设计这些物理IO既昂贵又耗时。如果没有一个通用的标准，异构组件就无法轻松集成，设计人员需要保守地预留较大的设计余量，这必然导致非最佳设计和成本增加。小芯片和封装之间的时序、功率和信号完整性属性也不能被传统的设计流程和CAD工具捕获。缺少低开销、低成本和可定制的IO和设计工具会大大减缓这些高级封装技术的采用。该项目使用芯片封装协同设计方法来联合收割机集成电路和封装设计，并为异构开发提供无缝环境。其目标是最大限度地减少小芯片间的性能开销，降低设计成本，探索2.5D系统的全部潜力，并展示最高的集成密度和能效。拟议的芯片设计工作和CAD工具将用于为学生提供教育材料、实践经验和客座讲座。该项目将通过在PI的机构和阿肯色州的一系列行业合作、大学预科教育、大学和研究生教育计划，为美国半导体研发领域急需的劳动力的发展做出贡献。该项目产生的设计工具将是开源的，并与设计示例和文档打包。该2.5D小芯片-封装协同设计流程将消除小芯片和封装之间的边界，并且联合收割机组合附加的设计合成、提取和优化步骤以最小化开销和成本。IO合成将根据详细的提取结果创建和放置大小刚好足够的小IO单元。有源封装合成将生成封装缓冲器和重定时器，以优化面积、线长和性能。芯片到封装耦合的整体和上下文提取将为同质和异质设计提供最高的准确性。2.5D系统的制造和测试旨在确保测量数据的真实验证。这一CAD流程将进一步打破低压和大功率工程之间的界限，并使计算机封装能够实现Si逻辑和GaN/SiC功率转换的异构集成。该奖项反映了NSF的法定使命，并通过使用基金会的智力价值和更广泛的影响审查标准进行评估，被认为值得支持。

Design of 2.5D chiplets is becoming increasingly popular as a flexible and scalable More-than-Moore solution to push computational performance of integrated circuit chips. With heterogeneous integration, each IP block can be implemented using the optimum technology node, maximizing design flexibility and performance. However, a drawback compared with a monolithic 2D chip is the large overhead introduced by inter-chiplet communication. On-package wires have much larger parasitics compared with on-chip interconnects. Thus, they may reduce the performance and energy-efficiency of 2.5D systems. Designing these physical IOs are expensive and time-consuming. Heterogeneous components cannot be easily integrated without a commonly used standard, and designers need to conservatively reserve a large design margin, which inevitably results in non-optimum designs and increased costs. The timing, power, and signal integrity properties between chiplets and the package are also not captured by the traditional design flow and CAD tools. The missing low-overhead, low-cost, and customizable IOs and design tools significantly slow down the adoption of these advanced packaging techniques. This project uses a chiplet-package co-design methodology to combine IC and package designs and provide a seamless environment for heterogeneous development. The goal is to minimize inter-chiplet performance overhead, reduce design costs, explore the full potential of 2.5D systems, and demonstrate the highest integration density and energy efficiency. The proposed chip design efforts and CAD tools will be used to provide educational materials, hands-on experience, and guest lectures to students. The project will contribute to the development of much needed US workforce in the area of research and development of semiconductors via a diverse set of plans for industry collaboration, pre-college education, and college and graduate-level education at the PI's institution, and in the state of Arkansas. The design tools resulting from the project will be open-sourced and packaged with design examples and documentation. This 2.5D chiplet-package co-design flow will eliminate the boundary between chiplets and the package and combine additional design synthesis, extraction, and optimization steps to minimize overhead and costs. The IO synthesis will create and place small IO cells with just-enough sizing based on detailed extraction results. The active package synthesis will generate on-package buffers and re-timers to optimize area, wirelength, and performance. Holistic and In-Context extraction for chiplet-to-package coupling will provide the highest accuracy for both homogeneous and heterogeneous designs. The fabrication and testing of 2.5D systems is intended to ensure realistic validation with measured data. This CAD flow will further break the boundary between low-voltage and high-power engineering and enable computer-on-package with heterogeneous integration of Si logic and GaN/SiC power conversion.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.