CAREER: SHF: Chiplet-Package Co-Optimizations for 2.5D Heterogeneous SoCs with Low-Overhead IOs

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Design of 2.5D chiplets is becoming increasingly popular as a flexible and scalable More-than-Moore solution to push computational performance of integrated circuit chips. With heterogeneous integration, each IP block can be implemented using the optimum technology node, maximizing design flexibility and performance. However, a drawback compared with a monolithic 2D chip is the large overhead introduced by inter-chiplet communication. On-package wires have much larger parasitics compared with on-chip interconnects. Thus, they may reduce the performance and energy-efficiency of 2.5D systems. Designing these physical IOs are expensive and time-consuming. Heterogeneous components cannot be easily integrated without a commonly used standard, and designers need to conservatively reserve a large design margin, which inevitably results in non-optimum designs and increased costs. The timing, power, and signal integrity properties between chiplets and the package are also not captured by the traditional design flow and CAD tools. The missing low-overhead, low-cost, and customizable IOs and design tools significantly slow down the adoption of these advanced packaging techniques. This project uses a chiplet-package co-design methodology to combine IC and package designs and provide a seamless environment for heterogeneous development. The goal is to minimize inter-chiplet performance overhead, reduce design costs, explore the full potential of 2.5D systems, and demonstrate the highest integration density and energy efficiency. The proposed chip design efforts and CAD tools will be used to provide educational materials, hands-on experience, and guest lectures to students. The project will contribute to the development of much needed US workforce in the area of research and development of semiconductors via a diverse set of plans for industry collaboration, pre-college education, and college and graduate-level education at the PI's institution, and in the state of Arkansas. The design tools resulting from the project will be open-sourced and packaged with design examples and documentation. This 2.5D chiplet-package co-design flow will eliminate the boundary between chiplets and the package and combine additional design synthesis, extraction, and optimization steps to minimize overhead and costs. The IO synthesis will create and place small IO cells with just-enough sizing based on detailed extraction results. The active package synthesis will generate on-package buffers and re-timers to optimize area, wirelength, and performance. Holistic and In-Context extraction for chiplet-to-package coupling will provide the highest accuracy for both homogeneous and heterogeneous designs. The fabrication and testing of 2.5D systems is intended to ensure realistic validation with measured data. This CAD flow will further break the boundary between low-voltage and high-power engineering and enable computer-on-package with heterogeneous integration of Si logic and GaN/SiC power conversion.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.