CAREER: SHF: Chiplet-Package Co-Optimizations for 2.5D Heterogeneous SoCs with Low-Overhead IOs

职业：SHF：具有低开销 IO 的 2.5D 异构 SoC 的 Chiplet 封装协同优化

• 批准号: 2047388
• 负责人: Yarui Peng
• 金额: $ 50万
• 依托单位: University of Arkansas
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2021
• 资助国家: 美国
• 起止时间: 2021-06-01 至 2026-05-31
• 项目状态: 未结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=2047388&HistoricalAwards=false
• 关键词: CAREER; SHF; Chiplet; Package; Co

Design of 2.5D chiplets is becoming increasingly popular as a flexible and scalable More-than-Moore solution to push computational performance of integrated circuit chips. With heterogeneous integration, each IP block can be implemented using the optimum technology node, maximizing design flexibility and performance. However, a drawback compared with a monolithic 2D chip is the large overhead introduced by inter-chiplet communication. On-package wires have much larger parasitics compared with on-chip interconnects. Thus, they may reduce the performance and energy-efficiency of 2.5D systems. Designing these physical IOs are expensive and time-consuming. Heterogeneous components cannot be easily integrated without a commonly used standard, and designers need to conservatively reserve a large design margin, which inevitably results in non-optimum designs and increased costs. The timing, power, and signal integrity properties between chiplets and the package are also not captured by the traditional design flow and CAD tools. The missing low-overhead, low-cost, and customizable IOs and design tools significantly slow down the adoption of these advanced packaging techniques. This project uses a chiplet-package co-design methodology to combine IC and package designs and provide a seamless environment for heterogeneous development. The goal is to minimize inter-chiplet performance overhead, reduce design costs, explore the full potential of 2.5D systems, and demonstrate the highest integration density and energy efficiency. The proposed chip design efforts and CAD tools will be used to provide educational materials, hands-on experience, and guest lectures to students. The project will contribute to the development of much needed US workforce in the area of research and development of semiconductors via a diverse set of plans for industry collaboration, pre-college education, and college and graduate-level education at the PI's institution, and in the state of Arkansas. The design tools resulting from the project will be open-sourced and packaged with design examples and documentation. This 2.5D chiplet-package co-design flow will eliminate the boundary between chiplets and the package and combine additional design synthesis, extraction, and optimization steps to minimize overhead and costs. The IO synthesis will create and place small IO cells with just-enough sizing based on detailed extraction results. The active package synthesis will generate on-package buffers and re-timers to optimize area, wirelength, and performance. Holistic and In-Context extraction for chiplet-to-package coupling will provide the highest accuracy for both homogeneous and heterogeneous designs. The fabrication and testing of 2.5D systems is intended to ensure realistic validation with measured data. This CAD flow will further break the boundary between low-voltage and high-power engineering and enable computer-on-package with heterogeneous integration of Si logic and GaN/SiC power conversion.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

2.5D芯片的设计作为一种灵活且可扩展的超过摩尔的解决方案正变得越来越流行，以推动集成电路芯片的计算性能。通过异类集成，每个IP块都可以使用最佳技术节点来实现，从而最大限度地提高设计灵活性和性能。然而，与单片2D芯片相比，一个缺点是芯片间通信引入了巨大的开销。与芯片上互连相比，封装内布线的寄生系数要大得多。因此，它们可能会降低2.5D系统的性能和能效。设计这些物理IO既昂贵又耗时。如果没有一个通用的标准，异质组件就不能很容易地集成在一起，设计人员需要保守地保留很大的设计余量，这不可避免地会导致设计不优化和成本增加。传统的设计流程和CAD工具也不能捕获芯片和封装之间的时序、功率和信号完整性属性。缺少低开销、低成本和可定制的IO和设计工具显著减缓了这些高级包装技术的采用。该项目使用芯片-封装联合设计方法，将IC和封装设计结合在一起，为异类开发提供了一个无缝环境。其目标是最大限度地减少芯片间性能开销，降低设计成本，发掘2.5D系统的全部潜力，并展示最高的集成密度和能效。建议的芯片设计工作和CAD工具将用于为学生提供教育材料、实践经验和客座讲座。该项目将通过一套多样化的行业合作计划、大学前教育计划以及国际半导体协会机构和阿肯色州的大学和研究生教育计划，为半导体研发领域急需的美国劳动力的发展做出贡献。该项目产生的设计工具将是开放源码的，并与设计实例和文档打包在一起。这种2.5D芯片封装联合设计流程将消除芯片和封装之间的界限，并结合额外的设计合成、提取和优化步骤，以最大限度地减少管理费用和成本。IO合成将根据详细的提取结果创建和放置大小适中的小型IO单元。主动封装合成将生成封装上的缓冲区和重定时器，以优化面积、有线长度和性能。芯片到封装耦合的整体和上下文提取将为同质和异质设计提供最高的准确性。2.5D系统的制造和测试旨在确保测量数据的真实性验证。这一CAD流程将进一步打破低电压和高功率工程之间的界限，实现硅逻辑和GaN/SiC功率转换的异类集成的封装计算机。该奖项反映了NSF的法定使命，并通过使用基金会的智力优势和更广泛的影响审查标准进行评估，被认为值得支持。

项目成果

Design Challenges of Intrachiplet and Interchiplet Interconnection

Chiplet 内和 Chiplet 间互连的设计挑战

• DOI: 10.1109/mdat.2022.3203005
• 发表时间: 2022
• 期刊: IEEE Design & Test
• 影响因子: 2
• 作者: Chen, Chixiao;Yin, Jieming;Peng, Yarui;Palesi, Maurizio;Cao, Wenxu;Huang, Letian;Singh, Amit Kumar;Zhi, Haocong;Wang, Xiaohang
• 通讯作者: Wang, Xiaohang