CRII: SHF: Design, Extraction, and Optimization of Multi-Chip Fan-Out Wafer-Level-Packaging for Low-Power Heterogeneous Systems

CRII：SHF：低功耗异构系统多芯片扇出晶圆级封装的设计、提取和优化

• 批准号: 1755981
• 负责人: Yarui Peng
• 金额: $ 17.5万
• 依托单位: University of Arkansas
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2018
• 资助国家: 美国
• 起止时间: 2018-07-01 至 2024-05-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1755981&HistoricalAwards=false
• 关键词: CRII; SHF; Design; Extraction; Optimization

With the slowing down of Moore's Law, it is challenging to integrate more transistors and features into a single chip. New system- and package-level techniques are critical for emerging mobile and Internet of Things (IoT) applications with a strong emphasis on power and cost. This research aims to develop the key models and Computer-Aided Design (CAD) tools to enable integrating various heterogeneous components into a single Fanout Wafer-Level Package. It will address the major challenge of maintaining signal integrity and electro-thermal reliability in a powerful, yet compact, system with multiple Integrated Circuits (ICs) closely packed together to improve energy and cost efficiency. Moreover, a graduate course on CAD and physical design will be offered at the University of Arkansas. The developed CAD framework will be open-sourced and publicly available to further stimulate the advancement in chip-package co-design tool flow and commercialization. With heterogeneous components tightly integrated, new parasitics, resulting from both electrical- and magnetic-coupling, require both IC and package designers to work together closely on circuit and physical design. The proposed CAD framework blurs the boundaries between chip and package layouts in the design flow and extracts major coupling elements between them. It integrates chip-package co-design techniques into the entire VLSI design flow with time-efficient computational models so that signal integrity issues can be captured and addressed early to avoid a time-consuming trial-and-error design process. All parasitic components such as coupling capacitance and mutual inductance are included to ensure accurate timing and noise analyses. The new modeling methods, CAD algorithms and flows, and optimization techniques address the principle motivation behind more-than-Moore technologies and move toward high-density and energy-efficient heterogeneous systems.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

随着摩尔定律的放缓，将更多的晶体管和功能集成到单个芯片中具有挑战性。新的系统级和封装级技术对于新兴的移动的和物联网（IoT）应用至关重要，这些应用非常注重功耗和成本。本研究旨在开发关键模型和计算机辅助设计（CAD）工具，以实现将各种异构组件集成到单个扇出晶圆级封装中。它将解决在一个强大而紧凑的系统中保持信号完整性和电热可靠性的主要挑战，该系统具有紧密封装在一起的多个集成电路（IC），以提高能源和成本效率。此外，阿肯色州大学将开设计算机辅助设计和物理设计研究生课程。开发的CAD框架将开源并公开，以进一步刺激芯片封装协同设计工具流程和商业化的进步。随着异构元件的紧密集成，由于电耦合和磁耦合而产生的新寄生效应要求IC和封装设计人员在电路和物理设计方面密切合作。建议的CAD框架模糊了芯片和封装布局之间的边界在设计流程中，并提取它们之间的主要耦合元素。它将芯片-封装协同设计技术集成到整个VLSI设计流程中，并具有高效的计算模型，因此可以及早捕获和解决信号完整性问题，以避免耗时的试错设计过程。包括耦合电容和互感等所有寄生元件，以确保精确的时序和噪声分析。新的建模方法、CAD算法和流程以及优化技术解决了超越摩尔技术背后的主要动机，并向高密度和高能效的异构系统迈进。该奖项反映了NSF的法定使命，并通过使用基金会的智力价值和更广泛的影响审查标准进行评估，被认为值得支持。

项目成果

Chiplet-Package Co-Design For 2.5D Systems Using Standard ASIC CAD Tools

使用标准 ASIC CAD 工具进行 2.5D 系统的小芯片封装协同设计

• DOI: 10.1109/asp-dac47756.2020.9045734
• 发表时间: 2020
• 期刊: 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC
• 作者: Kabir, MD Arafat;Peng, Yarui
• 通讯作者: Peng, Yarui

A Scalable In-Context Design and Extraction Flow for Heterogeneous 2.5D Chiplet-Package Co-Optimization

用于异构 2.5D Chiplet-Package 协同优化的可扩展上下文设计和提取流程

• DOI: 10.1109/epeps51341.2021.9609155
• 发表时间: 2021
• 期刊: IEEE Conference on Electrical Performance of Electronic Packaging and Systems
• 作者: Kabir, MD Arafat;Petranovic, Dusan;Peng, Yarui
• 通讯作者: Peng, Yarui

Coupling extraction and optimization for heterogeneous 2.5D chiplet-package co-design

异构 2.5D 小芯片封装协同设计的耦合提取和优化

• DOI: 10.1145/3400302.3415718
• 发表时间: 2020
• 期刊: International Conference On Computer Aided Design (ICCAD
• 作者: Kabir, MD Arafat;Petranovic, Dusan;Peng, Yarui
• 通讯作者: Peng, Yarui

Holistic and In-Context Design Flow for 2.5D Chiplet-Package Interaction Co-Optimization

• DOI: 10.1109/vlsi-dat52063.2021.9427353
• 发表时间: 2021-04
• 期刊: 2021 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)
• 作者: M. Kabir;Weishiun Hung;Tsung-Yi Ho;Yarui Peng

Cross-Boundary Inductive Timing Optimization for 2.5D Chiplet-Package Co-Design

2.5D Chiplet-Package 协同设计的跨界感应时序优化

• DOI: 10.1145/3453688.3461505
• 发表时间: 2021
• 期刊: Great Lakes Symposium on VLSI
• 作者: Kabir, MD Arafat;Petranovic, Dusan;Peng, Yarui
• 通讯作者: Peng, Yarui