CRII: SHF: Design, Extraction, and Optimization of Multi-Chip Fan-Out Wafer-Level-Packaging for Low-Power Heterogeneous Systems

随着摩尔定律的放缓，将更多的晶体管和功能集成到单个芯片中是一项挑战。新的系统级和封装级技术对于新兴的移动和物联网（IoT）应用至关重要，这些应用非常强调功率和成本。本研究旨在开发关键模型和计算机辅助设计（CAD）工具，以便将各种异构组件集成到单个扇出晶圆级封装中。它将解决在一个强大而紧凑的系统中保持信号完整性和电热可靠性的主要挑战，该系统采用多个集成电路（ic）紧密封装在一起，以提高能源和成本效率。此外，阿肯色大学将开设计算机辅助设计和物理设计的研究生课程。开发的CAD框架将是开源和公开的，以进一步刺激芯片封装协同设计工具流程和商业化的进步。由于异质元件紧密集成，电耦合和磁耦合导致的新寄生要求IC和封装设计人员在电路和物理设计上紧密合作。提出的CAD框架模糊了设计流程中芯片和封装布局之间的界限，并提取了它们之间的主要耦合元素。它将芯片封装协同设计技术集成到整个VLSI设计流程中，并采用高效的计算模型，以便及早捕获和解决信号完整性问题，避免耗时的试错设计过程。所有寄生元件，如耦合电容和互感都包括在内，以确保准确的定时和噪声分析。新的建模方法、CAD算法和流程以及优化技术解决了超越摩尔技术背后的主要动机，并朝着高密度和节能的异构系统发展。该奖项反映了美国国家科学基金会的法定使命，并通过使用基金会的知识价值和更广泛的影响审查标准进行评估，被认为值得支持。

With the slowing down of Moore's Law, it is challenging to integrate more transistors and features into a single chip. New system- and package-level techniques are critical for emerging mobile and Internet of Things (IoT) applications with a strong emphasis on power and cost. This research aims to develop the key models and Computer-Aided Design (CAD) tools to enable integrating various heterogeneous components into a single Fanout Wafer-Level Package. It will address the major challenge of maintaining signal integrity and electro-thermal reliability in a powerful, yet compact, system with multiple Integrated Circuits (ICs) closely packed together to improve energy and cost efficiency. Moreover, a graduate course on CAD and physical design will be offered at the University of Arkansas. The developed CAD framework will be open-sourced and publicly available to further stimulate the advancement in chip-package co-design tool flow and commercialization. With heterogeneous components tightly integrated, new parasitics, resulting from both electrical- and magnetic-coupling, require both IC and package designers to work together closely on circuit and physical design. The proposed CAD framework blurs the boundaries between chip and package layouts in the design flow and extracts major coupling elements between them. It integrates chip-package co-design techniques into the entire VLSI design flow with time-efficient computational models so that signal integrity issues can be captured and addressed early to avoid a time-consuming trial-and-error design process. All parasitic components such as coupling capacitance and mutual inductance are included to ensure accurate timing and noise analyses. The new modeling methods, CAD algorithms and flows, and optimization techniques address the principle motivation behind more-than-Moore technologies and move toward high-density and energy-efficient heterogeneous systems.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.