FET: Small: CMOS+X: Integration of CMOS and voltage-controlled magnetic tunnel junctions for probabilistic computing

FET：小型：CMOS X：集成 CMOS 和压控磁隧道结，用于概率计算

• 批准号: 2322572
• 负责人: Pedram Khalili Amiri
• 金额: $ 50万
• 依托单位: Northwestern University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2023
• 资助国家: 美国
• 起止时间: 2023-10-01 至 2026-09-30
• 项目状态: 未结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=2322572&HistoricalAwards=false
• 关键词: FET; Small; CMOS+X; Integration; CMOS

The fast growth of artificial intelligence applications currently outpaces the advances in their underlying semiconductor-based hardware. As a result, there is an urgent need for improved machine learning (ML) chips, which provide superior energy efficiency, reliability and security compared to existing solutions. At the same time, even with the best available computing hardware today, many important optimization problems cannot be solved using known algorithms in an efficient and scalable manner. Examples are the Boolean satisfiability, traveling salesman, and integer factorization problems, which have important applications ranging from microelectronic chip design to drug discovery, logistics, transportation, and cryptography. This project aims to develop application-specific integrated circuit (ASIC) prototypes that solve these problems using the physics of appropriately designed probabilistic circuits. These ASICs represent a physics-inspired and domain-specific computing architecture, where hardware and software are co-designed to solve a specific problem which cannot be efficiently solved – using finite time and energy resources – on any general-purpose classical computing chip. The project is expected to impact a wide range of artificial intelligence and optimization applications across various industries, while also providing new fundamental insights into the emerging class of probabilistic computing architectures. In addition to its research objectives, a key goal of this project is also workforce development for advanced semiconductor technologies. Research results will also be incorporated into new course materials being developed at Northwestern University.This project will develop integrated circuits where complementary metal-oxide silicon (CMOS) circuits are integrated with voltage-controlled magnetic memory devices, which will serve as ultrafast true random number generators. The chips are aimed for two application areas which will be investigated in this project: (A) Low-power machine learning processors based on probabilistic circuits: Convolutional neural networks require large numbers of transistors and high-power dissipation. The researchers will develop a stochastic computing implementation of neural networks integrated with magnetic memory devices, which simplifies the multiplication and addition operations, resulting in significant reduction of power consumption and chip area. (B) Combinatorial optimization processors based on probabilistic circuits: This project will also develop probabilistic optimization circuits where the optimization problem of interest is mapped onto an appropriately designed network of probabilistic bits on the ASIC. The performance and efficiency of the ASICs for both problems will be compared to existing general-purpose computing hardware.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

人工智能应用的快速增长目前超过了其基于半导体的底层硬件的进步。因此，迫切需要改进的机器学习(ML)芯片，与现有解决方案相比，这种芯片提供更高的能效、可靠性和安全性。同时，即使使用当今最好的计算硬件，许多重要的优化问题也不能以高效和可扩展的方式使用已知算法来解决。例如布尔可满足性问题、旅行商问题和整数分解问题，这些问题从微电子芯片设计到药物发现、物流、运输和密码学都有重要的应用。该项目旨在开发专用集成电路(ASIC)原型，使用适当设计的概率电路的物理学来解决这些问题。这些ASIC代表了一种受物理启发和特定领域的计算体系结构，其中硬件和软件共同设计，以解决无法在任何通用经典计算芯片上使用有限的时间和能量资源有效解决的特定问题。该项目预计将影响各个行业的广泛人工智能和优化应用，同时还将为新兴的概率计算架构提供新的基本见解。除了它的研究目标，这个项目的一个关键目标也是先进半导体技术的劳动力发展。研究成果也将被纳入西北大学正在开发的新课程材料中。该项目将开发互补金属氧化物硅(CMOS)电路与压控磁存储器件集成的集成电路，这将用作超高速真随机数发生器。该芯片针对两个应用领域：(A)基于概率电路的低功耗机器学习处理器：卷积神经网络需要大量的晶体管和高功耗。研究人员将开发一种与磁存储设备集成的神经网络的随机计算实现，该实现简化了乘法和加法运算，从而显著降低了功耗和芯片面积。(B)基于概率电路的组合优化处理器：该项目还将开发概率优化电路，其中感兴趣的优化问题被映射到ASIC上适当设计的概率位网络上。ASIC在这两个问题上的性能和效率将与现有的通用计算硬件进行比较。该奖项反映了NSF的法定使命，并已通过使用基金会的智力优势和更广泛的影响审查标准进行评估，被认为值得支持。