Source-synchronous I/O links using Adaptive Interface Trainings for High Bandwidth Applications

由于对计算的需求不断增加，如今在数据通信系统的各个级别都需要高带宽通信。通常，使用两种用于发送和接收高速数据的时钟方案：时钟数据恢复（CDR）和源同步。尽管CDR系统目前由于较高的符号率而实现了较高的每通道数据吞吐量，但其限制是在接收器侧恢复时钟的高努力以及高功率需求。源同步时钟用于并行接口，传输一个或多个时钟，不需要接收器PLL，因此本质上比CDR技术更鲁棒。需要克服的问题是信道非理想性（串扰、ISI、信号完整性，特别是时钟和数据之间的相位关系）。CDR在吞吐量方面提供了上级的每通道性能，而如果使用并行链路（多达32个或更多个信道），则源同步数据传输在吞吐量、功率和电路简单性方面可以是上级的。本研究计划旨在探讨各种方法的组合，以提高信源同步系统的数据速率，例如使用数字单位延迟增量器的节能时钟同步方案，采用超越最新技术水平的自适应均衡器训练算法（LMS均衡），用于差分和单端I/O系统的高级混合I/O校准算法，数据编码，特别是单端I/O，特别是单个测量的组合。由于之前在系统建模和抽象电路层面所做的工作，我们预计功率效率约为1 mW/Gbps或更好，但需要通过在硅演示器中演示这些方法的组合来证明。本研究建议，我们的目标是调查的源同步通信方法的原则边界。该研究建议的结果可用于各种场景，从片上数据通信，Chip-PCB-Chip和基于电缆的灵活连接。

Due to rising demand on computation, high bandwidth communication is nowadays required at all levels of data communication systems. In general, two clocking schemes for transmitting and receiving high speed data are used: clock-data-recovery (CDR) and source-synchronous. Whereas CDR systems currently achieve higher per lane data throughput due to the higher symbol rate, its limitations are the high effort and also high power need for recovering the clock at the receiver side. Source synchronous clocking is used for parallel interfaces, transmits one or more clocks, does not need a receiver PLL and is therefore inherently more robust than CDR techniques. The problems that need to be overcome are channel nonidealities (crosstalk, ISI, Signal Integrity and especially the phase-relationship between clock and data). Whereas CDR provides superior per lane performance regarding throughput, source-synchronous data transmission can be superior regarding throughput, power and circuit simplicity if parallel links (up to 32 or more channels) are used. This research proposal aims to investigate the combination of various methods for increasing the data rate of source synchronous systems, such as energy efficient clock synchronization scheme using a digital unit-delay incrementer, employing adaptive algorithms for equalizer training beyond state-of-the-art (LMS equalization), Advanced hybrid I/O calibration algorithms for differential and single-ended I/O-systems, Data encoding especially for single-ended I/Os, and especially the combination of the individual measures. Due to the previous work done at system modeling and abstract circuit level we expect a power efficiency of about 1mW/Gbps or better, but need the proof by demonstrating the combination of the approaches in a silicon demonstrator. With this research proposal we aim to investigate the principle boundaries of the source-synchronous communication approach. The results of this research proposal can be used in various scenarios, from on-chip data communications, Chip-PCB-Chip and flexible, cable-based connections.