Source-synchronous I/O links using Adaptive Interface Trainings for High Bandwidth Applications

由于对计算能力的要求越来越高，各级数据通信系统都需要高带宽通信。一般来说，收发高速数据的时钟方案有两种：时钟数据恢复（CDR）和源同步。虽然CDR系统目前由于更高的符号率而实现了更高的每通道数据吞吐量，但它的局限性是在接收端恢复时钟的高努力和高功率需求。源同步时钟用于并行接口，传输一个或多个时钟，不需要接收器锁相环，因此本质上比CDR技术更健壮。需要克服的问题是信道非理想性（串扰、ISI、信号完整性，特别是时钟和数据之间的相位关系）。虽然CDR在吞吐量方面提供了优越的每通道性能，但如果使用并行链路（最多32个或更多通道），源同步数据传输在吞吐量、功率和电路简单性方面可能更优越。本研究计划旨在研究提高源同步系统数据速率的各种方法的组合，例如使用数字单位延迟增量器的节能时钟同步方案，采用超越最先进（LMS均衡）的均衡器训练的自适应算法，差分和单端I/O系统的高级混合I/O校准算法，特别是单端I/O的数据编码，尤其是各个指标的结合。由于之前在系统建模和抽象电路级别所做的工作，我们预计功率效率约为1mW/Gbps或更高，但需要通过在硅演示器中演示这两种方法的组合来证明。本研究计划旨在探讨源同步通信方法的基本边界。本研究计划的结果可用于各种场景，从片上数据通信，芯片- pcb -芯片和灵活的，基于电缆的连接。

Due to rising demand on computation, high bandwidth communication is nowadays required at all levels of data communication systems. In general, two clocking schemes for transmitting and receiving high speed data are used: clock-data-recovery (CDR) and source-synchronous. Whereas CDR systems currently achieve higher per lane data throughput due to the higher symbol rate, its limitations are the high effort and also high power need for recovering the clock at the receiver side. Source synchronous clocking is used for parallel interfaces, transmits one or more clocks, does not need a receiver PLL and is therefore inherently more robust than CDR techniques. The problems that need to be overcome are channel nonidealities (crosstalk, ISI, Signal Integrity and especially the phase-relationship between clock and data). Whereas CDR provides superior per lane performance regarding throughput, source-synchronous data transmission can be superior regarding throughput, power and circuit simplicity if parallel links (up to 32 or more channels) are used. This research proposal aims to investigate the combination of various methods for increasing the data rate of source synchronous systems, such as energy efficient clock synchronization scheme using a digital unit-delay incrementer, employing adaptive algorithms for equalizer training beyond state-of-the-art (LMS equalization), Advanced hybrid I/O calibration algorithms for differential and single-ended I/O-systems, Data encoding especially for single-ended I/Os, and especially the combination of the individual measures. Due to the previous work done at system modeling and abstract circuit level we expect a power efficiency of about 1mW/Gbps or better, but need the proof by demonstrating the combination of the approaches in a silicon demonstrator. With this research proposal we aim to investigate the principle boundaries of the source-synchronous communication approach. The results of this research proposal can be used in various scenarios, from on-chip data communications, Chip-PCB-Chip and flexible, cable-based connections.