A novel high-speed and low power ADC based on a tracking ADC suitable for the implementation in general ultradeepsubmicron technologies

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A/D-Converter translate analogue electrical signals in digital information and are therefore an indispensable component for any communication system. Tracking-ADCs use comparably few analog components and are therefore quite suitable for the implementation in modern short-channel technologies, but suffer from limited Sample-Rates. With this project proposal we would like to investigate a new ADC-concept which is after first thoughts superior (regarding Sample-Rate, resolution and power consumption) to existing SAR or tracking-ADCs, but is avoiding at the same time the known limitations of sigma-delta-ADCs, and is still due to the almost exclusive implementation in digital logic economically suitable for the implementation in modern, state-of-the art technologies. With this project proposal the until now not challenged assumption for tracking-ADCs should be discontinued that the comparator immediately after detecting the input signal exceeding its comparative signal is inverting the counting direction of the digital counter. We would like to scientifically investigate and show that with the elimination of this fundamental assumption the technical properties of this modified tracking-ADCs (especially the maximum trackable slope, maximum input signal frequency as well as the resolution) likely improve significantly. After first thoughts, the existing design challenges on system and component level are modified: especially the comparator properties offset and high linearity also for large input signals now become top priorities, whereas the propagation delay steps back in importance. Further scientific investigations are now the optimal system properties of the digital signal processing network as well as the symmetry of the analog feedback signal. In the frame of this project system and component properties should be analysed, and ideally the fundamental concept is verified by fabrication and measurement of ideally two ASIC-implementations on a smaller than 28nm channel length / feature size technology.