VLSI Implementation of New Architectures Using High-Level Synthesis System-Design of Multithreaded Processor

在本项目中，我们尝试了一种基于多线程处理的处理器的VLSI实现，旨在提高数字图像生成的处理速度。多线程处理器具有多个指令解码器和寄存器堆来执行多个指令流(线程)，多个线程共享功能单元以获得高运行率。虽然该体系结构具有高性价比和高性能，但由于共享功能单元上多线程的控制非常复杂，使得设计变得困难，目前还没有相关的实现报道，我们利用高级综合系统来解决这个问题，用行为描述语言设计处理器的控制单元，然后通过综合系统将其编译成硬件。该方法极大地降低了设计复杂度，使多线程处理器的VLSI实现成为可能。我们还对这种方法进行了研究，提出了一种新的高级综合算法、用于逻辑综合的高效存储的逻辑函数数据结构，以及一种系统的VLSI版图模块聚类方法。

In this project, we attempted VLSI implementation of processors based on a new architecture called multithreaded processing, which aims at boosting the processing speed of digital image generation.A multithreaded processor has multiple instruction decoders and register files to execute multiple instruction streams (threads), with functional units shared by the threads for high operating ratio. Although the architecture is both cost-effective and high in performance, there had been no reported implementation because the control of multiple threads on shared functional units was highly complicated and thus made the design difficult.We made use of high-level synthesis system to meet this problem ; we designed the control unit of the processor in behavioral specification language and then compile them into hardware by the synthesis system. This approach significantly the reduced the design complexity and made the VLSI implementation of a multithreaded processor possible.We also made investigation to support this approach ; we developed a new algorithm for high-level synthesis, highly memory efficient data structure of logic function for logic synthesis, and an systematic approach for module clustering in VLSI layout.