VLSI Implementation for Digital Video Transmission and Compression

在这个项目中，我们开发了用于视频压缩的新体系结构和用于视频传输的数字滤波器。在视频压缩方面，我们开发了一种基于专用硬件组件的HDTV级MPEG2编/解码器的体系结构。我们首先为视频编解码的每个过程设计一个定制的硬件模块，然后将它们连接到经过优化配置的专用网络和存储器。在数字滤波器方面，我们开发了一种为数字滤波器定制的新的乘法算法，并实现了一个FIR作为VLSI。该算法利用了1)对于数字滤波器来说只有8到12位的精度就足够了，2)乘数可以是一个常系数，只要它是可编程的，并且该算法可以用很少的硬件实现。将11抽头的FIR滤波器实现为工作频率为100 MHz的单片VLSI，并研究了便于VLSI设计的高级综合系统。我们开发了一种系统，该系统可以利用现有的逻辑综合和版图工具，将用C语言编写的规格说明综合成RT级的VHDL语言描述，并自动转换成版图。

In this project, we developed new architectures for video compression and digital filters for video transmission. We also attempted to implement VLSIs based on the architectures.As for video compression, we developed an architecture for HDTV level MPEG2 encoder/decoder based on dedicated hardware components. We first designed for each process of video encoding/decoding a customized hardware module and then connect them with dedicated networks and memories which are optimally configured. We succeeded in integrating the encoder/decoder facilities on two VLSI chips.As for digital filters, we developed a novel multiplication algorithm customized for digital filters and implemented a FIR as a VLSI.The algorithm enables very fast with small amount of hardware, making use of the fact that 1) only 8 to 12 bit precision is enough for the digital filters and 2) multiplicand may be a constant coefficient as long as it is programmable. An FIR filter of 11 taps is implemented as a single chip VLSI which operates at 100MHz.We also made investigation on high-level synthesis system which expediates the design of VLSI.We developed a system which synthesizes from a specification written in C-language an RT-level VHDL description, which can be transformed automatically into layout pattern using existing logic synthesis and layout tools.