VLSI Implementation for Digital Video Transmission and Compression

数字视频传输和压缩的 VLSI 实现

• 批准号: 08455178
• 负责人: SHIRAKAWA Isao
• 金额: $ 4.93万
• 依托单位: Osaka University
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for Scientific Research (B)
• 财政年份: 1996
• 资助国家: 日本
• 起止时间: 1996 至 1997
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-08455178/
• 关键词: digital signal processing; VLSI implementation; MPEG; FIR filter; ディジタル記号処理; VLSI

In this project, we developed new architectures for video compression and digital filters for video transmission. We also attempted to implement VLSIs based on the architectures.As for video compression, we developed an architecture for HDTV level MPEG2 encoder/decoder based on dedicated hardware components. We first designed for each process of video encoding/decoding a customized hardware module and then connect them with dedicated networks and memories which are optimally configured. We succeeded in integrating the encoder/decoder facilities on two VLSI chips.As for digital filters, we developed a novel multiplication algorithm customized for digital filters and implemented a FIR as a VLSI.The algorithm enables very fast with small amount of hardware, making use of the fact that 1) only 8 to 12 bit precision is enough for the digital filters and 2) multiplicand may be a constant coefficient as long as it is programmable. An FIR filter of 11 taps is implemented as a single chip VLSI which operates at 100MHz.We also made investigation on high-level synthesis system which expediates the design of VLSI.We developed a system which synthesizes from a specification written in C-language an RT-level VHDL description, which can be transformed automatically into layout pattern using existing logic synthesis and layout tools.

在该项目中，我们开发了用于视频压缩的新架构和用于视频传输的数字滤波器。在视频压缩方面，我们开发了一种基于专用硬件器件的HDTV级MPEG 2编解码器的体系结构。我们首先为每个视频编码/解码过程设计了一个定制的硬件模块，然后将它们与优化配置的专用网络和存储器连接。我们成功地将编码器/解码器设备集成在两个VLSI芯片上。至于数字滤波器，我们开发了一种为数字滤波器定制的新颖乘法算法，并将FIR实现为VLSI。该算法可以用少量硬件实现非常快的速度，利用以下事实：1）仅8至12位精度对于数字滤波器是足够的，以及2）被乘数可以是常数系数，只要它是可编程的。在此基础上，本文还研究了一种高级综合系统，该系统能从C语言的规范中综合出一个RT级的VHDL描述，并能利用现有的逻辑综合和版图设计工具将其自动转换成版图。

项目成果

K.Miyanohana: "Implementation of Very Low Bitrate Video Encoder Core" Proc.2nd International Conference on ASIC. 131-134 (1996)

K.Miyanohana：“极低比特率视频编码器核心的实现”Proc.2nd 国际 ASIC 会议。

K.Miyanohana: "VLSI Implementation of Single Chip Encoder/Decoder for Low Bitrate Visual Communication" Proc.IEEE Costom Integrated Circuits Conference. 229-232 (1997)

K.Miyanohana：“用于低比特率视觉通信的单芯片编码器/解码器的 VLSI 实现”Proc.IEEE Costom 集成电路会议。

S.NAKAMURA N.ISHIURA et al.: "High-Lecal Syrthosis System for Behaveioral Deseriptions with Conditional Brandet" Proc.ITC-CSCC. Vol.1. 935-938 (1996)

S.NAKAMURA N.ISHIURA 等人：“带有条件 Brandet 的行为描述的 High-Lecal Syrthosis 系统”Proc.ITC-CSCC。

T.Onoye: "A VLSI Architecture of MPEG2 MP@HL Motion Estimator" Proc.IEEE Int′l Symposium on Circuits and Systems. 664-667 (1996)

T. Onoye：“MPEG2 MP@HL 运动估计器的 VLSI 架构”Proc。IEEE 国际电路与系统研讨会 664-667 (1996)。

K.Miyanohana: "VLSI Architecture for Very Low Bitrate Video Encoder Core" Proc.Int′l Technical Conference on Circuits/Systems,Computers and Communications. 294-297 (1996)

K.Miyanohana：“极低比特率视频编码器核心的 VLSI 架构”Proc.Intl 电路/系统、计算机和通信技术会议 294-297 (1996)。