VLSI Architecture for Video Codec Based on Discrete Wavelet Transform

基于离散小波变换的视频编解码VLSI架构

• 批准号: 12450153
• 负责人: SHIRAKAWA Isao
• 金额: $ 4.67万
• 依托单位: Osaka University
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for Scientific Research (B)
• 财政年份: 2000
• 资助国家: 日本
• 起止时间: 2000 至 2001
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/en/grant/KAKENHI-PROJECT-12450153/
• 关键词: discrete wavelet transform; VLSI; low power; retargetable compiler; ウエーブレット変換; 画像圧縮; MPEG-4; JPEG2000

In this project, we developed VLSI architecture for video codec based on discrete wavelet transform. We developed a wavelet based algorithm for scalable still-image and video compression. The algorithm adopts a modified 2-D subband decomposition scheme in conjunction with a partial zerotree search for efficient Embedded Zerotree Wavelet coding. In spite of the performance inferiority to teh conventional DWT, the algorithm attains significant reduction of DWT memory requirements, enhancing a reasonable balance between implementation cost and image quality.Furthermore, we implemented an MPEG-4 audio decoder, which is dedicated to portable audio appliances. Based on the results of sound quality evaluation, a low-power architecture is devised by means of frame-level pipeline and optimization of functional datapath. The proposed MPEG-4 audio decoder has been implemented with the use of 0.25 μm CMOS library, which integrates 30 k gates and dissipates 4.54 mW at 2.5 V supply.

在这个项目中，我们开发了基于离散小波变换的视频编解码器的VLSI架构。我们开发了一种基于小波的算法，用于可扩展的静态图像和视频压缩。该算法采用改进的二维子带分解方案并结合部分零树搜索来实现高效的嵌入式零树小波编码。尽管性能不如传统的DWT，但该算法显着降低了DWT内存需求，增强了实现成本和图像质量之间的合理平衡。此外，我们实现了专用于便携式音频设备的MPEG-4音频解码器。基于声音质量评估的结果，通过帧级流水线和功能数据路径的优化设计了低功耗架构。所提出的 MPEG-4 音频解码器已使用 0.25 μm CMOS 库实现，该库集成了 30 k 个门，在 2.5 V 电源下功耗为 4.54 mW。

项目成果

M.Furuie: "Two-Dimensional Array Layout for Low Power NMOS 4-Phase Dynamic Logic"Proc. Int'l Conf. on Electronics Packaging. 417-421 (2001)

M.Furuie：“低功耗 NMOS 4 相动态逻辑的二维阵列布局”Proc。

N. Ishiura, T. Watanabe, and M. Yamaguchi: "A Code Generation Method for Datapath Oriented Application Specific Processor Design"Proc. Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI 2000), Kyoto, Japan. 71-78 (2000)

N. Ishiura、T. Watanabe 和 M. Yamaguchi：“面向数据路径的专用处理器设计的代码生成方法”Proc。

N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa: "DSP Implementation of 3D Sound Localization Algorithm for Monaural Sound Source"Proc. The 8th IEEE International Conference on Electronics, Circuits and Systems(ICECS 2001), Malta. 1061-1064 (2001)

N. Sakamoto、W. Kobayashi、T. Onoye 和 I. Shirakawa：“单声道声源 3D 声音定位算法的 DSP 实现”Proc。

M.Furuie: "Two-Dimensional Array Layout for Low Power NMOS 4-Phase Dynamic Logic"Proc.Int'l Conf.on Electronics Packaging. 417-421 (2001)

M.Furuie：“低功耗 NMOS 4 相动态逻辑的二维阵列布局”Proc.Intl Conf.on 电子封装。

S.Hashimoto: "VLSI Impplementation of Portable MPEG-4 Audio Decorder"Proc. Int'l ASIC/SOC Conference. 80-84 (2000)

S.Hashimoto：“便携式 MPEG-4 音频解码器的 VLSI 实现”Proc。