VLSI architecture for MPEG-4 Audio Visual Codec

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In this project, we developed new architectures for MPEG-4 audio and video compression for wireless communication. We also attempted to implement VLSIs based on the architectures. We developed an architecture for H.324 encoder/decode, which is closely related to MPEG-4, based on dedicated hardware components. A number of sophisticated low-power architectures have been devised dedicatedly for the mobile use. A set of specific functional units, each corresponding to a process of H.263 video codec, is employed to lighten different performance bottlenecks. A compact DSP core composed of two MAC units is used for both ACELP and MP-MLQ coding schemes of the G.723.1 speech codec. The designed audiovisual codec core has been implemented by using 0.35μm CMOS 4LM technology, which contains totally 420k transistors with the dissipation of 224.32mW from single 3.3V supply.Furthermore, we implementated an MPEG-4 audio decoder, which is dedicated to portable audio appliances. Based on the results of sound quality evaluation, we devise a low-power architecture for each module such as utilization of frame-level pipeline architecture, optimization of functional datapath, etc.We developed a retargetable compiler which is used for application specific DSPs, such as the G.723.1 speech codec DSP.