VLSI architecture for MPEG-4 Audio Visual Codec

MPEG-4 音频视频编解码器的 VLSI 架构

• 批准号: 10450151
• 负责人: SHIRAKAWA Isao
• 金额: $ 3.84万
• 依托单位: Osaka University
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for Scientific Research (B)
• 财政年份: 1998
• 资助国家: 日本
• 起止时间: 1998 至 1999
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-10450151/
• 关键词: MPEG-4; VLSI implementation; low power; retargetable compiler; DSP; リターゲッタブルコンパイラ; MPEG4; コンパイラ

In this project, we developed new architectures for MPEG-4 audio and video compression for wireless communication. We also attempted to implement VLSIs based on the architectures. We developed an architecture for H.324 encoder/decode, which is closely related to MPEG-4, based on dedicated hardware components. A number of sophisticated low-power architectures have been devised dedicatedly for the mobile use. A set of specific functional units, each corresponding to a process of H.263 video codec, is employed to lighten different performance bottlenecks. A compact DSP core composed of two MAC units is used for both ACELP and MP-MLQ coding schemes of the G.723.1 speech codec. The designed audiovisual codec core has been implemented by using 0.35μm CMOS 4LM technology, which contains totally 420k transistors with the dissipation of 224.32mW from single 3.3V supply.Furthermore, we implementated an MPEG-4 audio decoder, which is dedicated to portable audio appliances. Based on the results of sound quality evaluation, we devise a low-power architecture for each module such as utilization of frame-level pipeline architecture, optimization of functional datapath, etc.We developed a retargetable compiler which is used for application specific DSPs, such as the G.723.1 speech codec DSP.

在这个项目中，我们开发了用于无线通信的MPEG4音频和视频压缩的新体系结构。我们还尝试实现基于体系结构的VLSI。我们开发了一种与MPEG4密切相关的H.324编/解码体系结构，该体系结构基于专用的硬件组件。许多复杂的低功耗架构都是专门为移动应用而设计的。采用了一组特定的功能单元，每个功能单元对应于H.263视频编解码器的一个进程，以减轻不同的性能瓶颈。G.723.1语音编解码器的ACELP和MP-MLQ两种编码方案都使用了一个由两个MAC单元组成的紧凑型DSP核。采用0.35μm CMOS4LM工艺实现了音视频编解码芯片，该芯片共包含420K晶体管，3.3V单电源功耗为224.32 mW，并实现了一款便携式音频设备专用的MPEG4音频解码器。根据音质评估的结果，我们为每个模块设计了低功耗的体系结构，如使用帧级流水线结构、优化函数数据路径等，并开发了适用于特定应用的编译器，如G.723.1语音编解码器DSP。

项目成果

H. Okuhata: "A Low-Power DSP Core Architecture for Low Bitrate Speech Codec"IEICE Trans. Fundamentals. E81-C. 1616-1621 (1998)

H. Okuhata：“用于低比特率语音编解码器的低功耗 DSP 核心架构”IEICE Trans。

H. Fujishima: "Hibrid Media-Processor Core for Natural and Synthetic Video Decoding"Proc. IEEE Int'l Symposium on Circuits and Systems. 572-575 (1999)

H. Fujishima：“用于自然和合成视频解码的混合媒体处理器核心”Proc。

K. Matsumura, G. Fujita, I. Shirakawa, and H. Inada: "A Wireless Data System Constructed of SAW-Based Receiver/Transmitter and its Applications to Medical Cares"Proc. IEEE Radio ω Wireless Conf.. 47-50 (1998)

K. Matsumura、G. Fujita、I. Shirakawa 和 H. Inada：“基于 SAW 的接收器/发射器构建的无线数据系统及其在医疗保健中的应用”Proc. IEEE Radio omega Wireless Conf. 47-50 ( 1998）

G.Fujita,T.Onove,I.Shirakawa: "A VLSI Architecture for Motion Estimation Core Dcdicated to H.263 Video Coding" IEICE Trans.Electronics. E81-C,5. 702-707 (1998)

G.Fujita、T.Onove、I.Shirakawa：“专用于 H.263 视频编码的运动估计核心的 VLSI 架构”IEICE Trans.Electronics。

K. Matsumura, G. Fujita, I. Shirakawa, and H. Inada: "A Wireless Data System by Means of SAW-Based Transmitter/Receiver and its Applications to Medical Cares"Proc. International Technical Conference on Circuits/Systems, Computers and Communications. 299-3

K. Matsumura、G. Fujita、I. Shirakawa 和 H. Inada：“基于 SAW 的发射器/接收器的无线数据系统及其在医疗保健中的应用”Proc。