High-Performance Processor Design for Image Processing

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A novel design famework is proposed for exploring JPEG2000 encoder architecture. Through the use of this framework, a designer can implement various types of JPEG2000 encoders referring to its specification, i.e. image resolution, performance requirements, power consumption, fabrication technology, chip size limitation. In order to utilize the scalablility of JPEG2000 algorithm aggressively, each procedure of JPEG2000 encoding is selectively implemented in this framework among those by software, software accelerated with user-defined instructions, or dedicated hardware. To embody such a Plug-and-Play like feature, each hardware module is designed to have a generic SRAM-based interface which can support various bus architectures by only designing interface converters. Therefore, our framework makes it much easier to design a JPEG2000 encoding system than conventional tedious manual design tasks of each procedure, which would be implemented as software or hardware. Dedicated hardware modules as well as software acceleration are devised to be used in the framework, and an LSI is fabricated to exemplify the system implementation designed through the use of our framework.