Precise Fine-Pattern-Etching of Resist Using Supermagnetron Plasma

随着半导体集成电路集成密度的提高，对亚微米蚀刻技术提出了更高的要求。为了发展256MbDRAM，需要0.2 μ m的精细蚀刻。今后2-5年后，将启动1Gb-4GbDRAM的研究和O. 15-0.2 μ m精细图案蚀刻的研究。在这项为期两年的1mum厚阻高速率蚀刻研究中，研究人员使用了大约五年前由首席研究员开发的超磁控管等离子体蚀刻机，用于工业应用。通过低温循环器将下阴极和衬底冷却至-30ºC来控制蚀刻形状。上阴极用石墨板覆盖，以防止溅射金属沉积污染衬底表面。经氧等离子体蚀刻的石墨转变为CO气体，不会污染衬底。为了制备精细图案蚀刻，在-20℃左右的较低阴极温度下，研究了多种蚀刻特性。在上阴极和下阴极的射频功率相差约180时，获得了最高的刻蚀速率和刻蚀均匀性。在O_2气体流量为30 ~ 50 sccm时，可获得0.5 ~ 1mum/min的高刻蚀速率。利用准分子激光曝光设备在硅片上刻蚀含有硅的光刻胶。在-140V的自偏置电压下，将晶圆冷却至-20ºC，在0.02 μ m的小侧壁蚀刻范围内刻蚀出具有垂直侧壁的0.25 μ m线。研究结果表明，利用超磁控管等离子体可以实现为未来ULSI工艺所研究的0.1 μ m精细图案刻蚀技术。

With increase of the integration density of semiconductor integrated circuits, submicron pattern etchings were required. For the development of 256MbDRAM, 0.2mum fine pattern etchings would be necessary. After 2-5 years from now, the research of 1Gb-4GbDRAM and the study of O. 15-0.2mum fine pattern etchings will be started. In this two-years study of high-rate etching of 1mum thick resist, a supermagnetron plasma etcher developed about five years ago by the head investigator was used for its application to the industry use. The etch shape was controlled by chilling the lower cathode and substrates down to -30ﾟC using a low temperature circulator. The upper cathode was covered with a graphite plate to prevent from the contamination of the substrate surface by the deposition of sputtered metals. The graphite etched by oxigen plasma changes to CO gas and never contaminate the substrate.For the preparation of fine pattern etching, many kinds of etching characteristics were investigated at the lower cathode temperature of about -20ﾟC. The highest etch-rate and etch-uniformity were obtained at the rf phase difference of about 180ﾟ between the rf powers supplied to the upper and lower cathodes. The high etch rates of 0.5-1mum/min were obtained at the O_2 gas flow rate of 30-50 sccm. The resist layers on Si wafers, patterned with Si containing photoresist by using eximer laser exposure equipment, were etched. 0.25mum lines with vertical side walls were etched within a small side wall etching of 0.02mum by chilling the wafer down to -20ﾟC at the self-bias voltage of -140V. From this study, it was found that the 0.1mum fine pattern etching technology investigated for for the future ULSI process could be realized using the supermagnetron plasma.