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Development of On-chip Nano-Scale Network Based on Communication Theory

基于通信理论的片上纳米级网络的研制

基本信息

批准号：
16206034
负责人：
MASU Kazuya
金额：
$ 31.87万
依托单位：
Tokyo Institute of Technology
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (A)
财政年份：
2004
资助国家：
日本
起止时间：
2004 至 2007
项目状态：
已结题

来源：
https://kaken.nii.ac.jp/en/grant/KAKENHI-PROJECT-16206034/
关键词：
transmission line integrated cirtcuit nano interconnect high speed signal propagation low power consumption system on chip network on chip wire length distribution

项目摘要

Si CMOS has been scaled according to the "Scaling Concept" and have achieved high performance, low power consumption, and high functionality. The Si CMOS has become the most important hardware in ubiquitous network. In 2013, hundred million transistors will be integrated on a one chip of 20mm square using 35nm technology and the operating frequency is expected to be over 20GHz. The Si CMOS is progressing toward Nano Scale era.In this work, the signal propagation is recognized to be just communication, and we have developed global wiring technology. The novel analytic expression has been derived for wire length distribution ; the wire length distribution and cumulative number of interconnects of real 130nm and 90nm CMOS chip are well expressed by our new model. We have developed global wiring technology based on differential transmission line ; 0.27pJ/bit transmission has been successfully achieved on 1cm long interconnect, and mutli drop transmission line interconnect has been also developed for future network on-chip technology. Furthermore, novel FoM (Figure of Merit) has been proposed to compare the performance of various interconnects ; the conventional RC line, the RC line using CNT (Carbon Nano Tube), transmission line interconnect which has been developed in this work, optical interconnect, and wireless interconnect. As a results, the FoM of the transmission line interconnect has most superior in the range of several hundred micron to several mm. This means the transmission line has been the best solution for global wiring.

硅CMOS已经根据“缩放概念”进行缩放，并且已经实现了高性能、低功耗和高功能。硅CMOS已成为泛在网络中最重要的硬件。到2013年，亿个晶体管将被集成在一个20平方毫米的芯片上，采用35纳米技术，工作频率预计将超过20 GHz。硅互补金属氧化物半导体正迈向奈米时代，在这项工作中，我们认识到信号的传播只是通信，并开发了全球布线技术。推导出了新的线长分布解析表达式，并对真实的130 nm和90 nm芯片的线长分布和累积互连线数进行了较好的描述。我们开发了基于差分传输线的全局布线技术;在1cm长的互连上成功实现了0.27pJ/bit的传输，并为未来的网络片上技术开发了多点传输线互连。此外，新的FoM（品质因数）已被提出来比较各种互连的性能;传统的RC线，使用CNT（碳纳米管）的RC线，传输线互连已在这项工作中开发，光学互连，和无线互连。结果表明，传输线互连的FoM在几百微米到几毫米的范围内具有最优越的上级性能，这意味着传输线已经成为全球布线的最佳解决方案。