ULTRA-LOW-POWER SILICON LSI DESIGN BASED ON Eb/No-BER CHARACTERISTICS

本课题的研究目的是建立基于“Eb/No-BER特性”的纳米级器件超低功耗设计的基础。“1.研制了硅CMOS测试芯片，并首次对其Eb/No-BER特性进行了评价。在此基础上，提出了适用于小型化CMOS电路的最小电源电压。此外，还对互连线间的串扰噪声进行了估计.将“Eb/No-BER特性”应用于单电子晶体管（SET）的设计。根据模拟结果，提出了基于“Eb/No-BER特性”的外围寄生电容和互连线布局作为纳米级器件设计的指导原则.从室温工作的角度研究了互补SET（CSET）反相电路。从“Eb/No-BER特性”可以看出，在现代制造技术下，室温CSET很难实现.从信噪比恢复的概念出发，首次提出了一种新的匹配滤波器型CSET，以代替普通的CSET。在室温下对由3片匹配滤波器组成的CSET进行了测试。虽然匹配滤波器类型的CSET已被证明是有效的S/N恢复，总功耗被发现上升。毕竟，从“Eb/No-BER特性”可以确认SET电路适用于低温工作，并且已经提出并研究了下一代超高速大容量总线，我们相信以上研究成果可以满足下一代超低功耗高速ULSI电路设计的要求。

The purpose of this research project is to establish the basis of ultra low power design of nano-scale devices on the basis of "Eb/No-BER characteristics."1. Silicon CMOS test chips have been fabricated and their Eb/No-BER characteristics have been evaluated for the first time. Base on the measurement results, the minimum supply voltage for miniaturized CMOS circuits is proposed. Furthermore, cross-talk noises among the wiring interconnects have been estimated.2. "Eb/No-BER characteristics" was applied to a design of single electron transistors (SET). From simulation results, peripheral parasitic capacitance and interconnect layout have been proposed as a guiding principle of nano-scale devices based on the "Eb/No-BER characteristics".3. Complementary SET (CSET) inverter circuits were investigated from the viewpoint of room temperature operation. From the "Eb/No-BER characteristics", it has been found that room-temperature CSET is hardly implemented under up-to-date manufacturing technology.4. Instead of normal CSET, novel matched filter type CSET has been proposed for the first time from a concept of S/N recovery. CSET which consists of 3chip matched filter has been evaluated at room temperature. Although matched filter type CSET has been proved to be effective for S/N recovery, total power consumption is found to go up. After all, it is confirmed from the "Eb/No-BER characteristics" that SET circuits is applicable to low-temperature operation.Furthermore, ultra high-speed high-capacity bus lines for the next generation have been proposed and investigated.We believe that the above achievements of this research fulfill the requirements for the next generation ultra low-power high-speed ULSI circuits design.