GHz Electromigration Endurance Evaluation of ULSI Interconnect

ULSI 互连的 GHz 电迁移耐久性评估

• 批准号: 13555090
• 负责人: MASU Kazuya
• 金额: $ 8.96万
• 依托单位: Tokyo Institute of Technology
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for Scientific Research (B)
• 财政年份: 2001
• 资助国家: 日本
• 起止时间: 2001 至 2002
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/en/grant/KAKENHI-PROJECT-13555090/
• 关键词: ULSI; Silicon; Interconnect; Electromigration; High Speed Signal Processing; Transmission Line Interconnect

The two major reliability issues of Si CMOS ULSI are (1) reliability of ultra thin gate insulator, and (2) EM(electromigration) endurance when a high density current is flowed through ultra fine interconnects. This research project is relating to the second issue. In 100nm and sub-100nm Si CMOS ULSIs, the EM issue is critical at the fine interconnect with several tens μm length. The conventional EM endurance is measured using DC current. On the other, in real ULSI, GHz pulse signal is flowed through the fine interconnect. It has been said that the EM endurance is improved at high frequency current condition. However, quantitative EM life time is not clarified. The purpose of this research project is to develop the interconnect structure which can measure GHz EM endurance. The measurement system for GHz signal through ULSI interconnect has been established. Using a 3D electromagnetic simulation, the transmission line interconnect has been designed, fabricated, and evaluated. Furthermore, driver circuit which drives the transmission line interconnect has been designed. From these results, the evaluation technology for GHz EM endurance has been established.

Si CMOS ULSI的两个主要可靠性问题是（1）超薄栅极绝缘体的可靠性，以及（2）当高密度电流流过超细互连时的EM（电迁移）耐久性。本研究项目涉及第二个问题。在100nm和亚100nm的硅CMOS ULSI中，EM问题在具有几十μm长度的精细互连处是关键的。传统的电磁耐受性是使用直流电流测量的。另一方面，在真实的ULSI中，GHz脉冲信号流经精细互连。据说在高频电流条件下提高了EM耐久性。然而，定量的EM寿命并不明确。本研究计画的目的是发展一种可量测GHz电磁波耐久度的互连结构。建立了ULSI互连线GHz信号的测试系统。使用三维电磁仿真，传输线互连的设计，制造和评估。此外，还设计了驱动传输线互连的驱动电路。根据这些结果，GHz电磁耐久性的评估技术已经建立。

项目成果

H. Ito, Shinichiro Gomi, Hirotaka Sugawara, K. Okada and K. Masu: "Low Crosstalk Differential Transmission Line Interconnect on Si ULSI"International Conference on Solid State Devices and Materials, Tokyo. submitted. (2003)

H. Ito、Shinichiro Gomi、Hirotaka Sukawara、K. Okada 和 K. Masu：“Si ULSI 上的低串扰差分传输线互连”固态器件和材料国际会议，东京。

高木直弘, 篠木日曜子, 益 一哉: "システムLSIにおける配線長分布"電子情報通信学会集積回路研究専門委員会第5回システムLSIワークショップ. 275-278 (2001)

Naohiro Takagi、Yoko Shinoki、Kazuya Masu：“系统 LSI 中的线长分布”IEICE 集成电路研究委员会第五届系统 LSI 研讨会 275-278 (2001)。

対馬朋人, 中村恒一, 益 一哉: "Si ULSIにおける伝送線路配線駆動の検討(II)-駆動回路の設計と試作-"2002年(平成14年)秋季第63回応用物理学会学術講演会. 26-F-8 (2002)

Tomoto Tsushima，Koichi Nakamura，Kazuya Masu：“Si ULSI中传输线布线驱动的研究（II）-驱动电路的设计和原型设计”2002年（平成14）秋季第63届日本应用物理学会学术会议.26-F-8 (2002)

H.Nakashima, N.Takagi, K.Masu: "Extraction of Interconnect-Length-Distribution Parameters from CAD Data"Advanced Metallization Conference 2002 : Asian Session, Tokyo, October 2002. (Proceedings volume to be publised). (2002)

H.Nakashima、N.Takagi、K.Masu：“从 CAD 数据中提取互连长度分布参数”2002 年高级金属化会议：亚洲会议，东京，2002 年 10 月。（会议记录卷待出版）。

H. Shinoki, H. Ito, Y. Yokoyama and K. Masu: "Transmission Line Interconnect Structure in Si ULSI"Advanced Metallization Conference 2002 : 12th Asian Session, Tokyo. (2002)

H. Shinoki、H. Ito、Y. Yokoyama 和 K. Masu：“Si ULSI 中的传输线互连结构”2002 年高级金属化会议：第 12 届亚洲会议，东京。