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"Investigation of Cold Electronics Semiconductor LSI"

《冷电子半导体LSI调查》

基本信息

批准号：
62420032
负责人：
MASU Kazuya
金额：
$ 21.06万
依托单位：
Tohoku University
依托单位国家：
日本
项目类别：
Grant-in-Aid for General Scientific Research (A)
财政年份：
1987
资助国家：
日本
起止时间：
1987 至 1990
项目状态：
已结题

来源：
https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-62420032/
关键词：
Cold Electronics Integrated Circuit Low Temperature Operation Thermal Capability Dynamic Thermal analysis Device Simulation Microchannel Fin Package Temperature Scaling マイクロチャネルフィンコールドエレクトロニクス

项目摘要

The integration density of VLSI is increasing year by year with the requirement of high speed and high density. It should be noted that, even at present time, the integration density of logic-VLSI which requires the large power dissipation for high speed operation is limited by the thermal capability of the chip. Although cryoelectronics based on the Josephson logic circuit is one of the high-speed and high-density LSI's, We notice that cold electronics based on Si VLSI technology is the most promising candidate which can break through the present limitation of VLSI. This research project was carried out under the following subjects :1. To develop a new package concept in which the thermal capability is one or two order larger than that of the conventional packages.2. To develop a new design principle of low-temperature operated high-speed Si MOSFET, and to fabricate basic MOS devices for low-temperature operation. In this research project, we carried out detailed work on cold electron … More ics for four years (1987-1990) and obtained the following results :1. We proposed "a microchannel fin package" utilizing an AIN passivation layer as the heat spreader inside the chip and a microchannel fin as the efficient heat removal method from the chip. Thermal capability of the new package was evaluated using our simulator of dynamic thermal analysis in two/three dimensions. When the water-cooled microchannel fin is used, the dissipation power in a VLSI chip is quite allowable as high as 1.5kW/cm^2. More than 500k-gate ECL circuits with 3mW per gate are sufficiently integrated on a 1-cm^2 chip. When a compressive-air-cooled microchannel fined, the dissipation power is allowable as high as 30W/cm^2. The thermal capability of the microchannel fin package is one or two order larger than that of the conventional package.2. We proposed a new scaling theory, "a temperature-scaling theory", relating to the operation temperature. Using our device simulator in two/three dimensions, we found that current-voltage characteristics were scaled down in proportion to the operation temperature, while the mobile-carrier distribution was kept constant. According to the temperature scaling theory, the optimum supply voltage for 0.1mum MOSFET is 1-1.5V and the gate delay times is estimated to be 1.6psec. Furthermore, we fabricated a LaB_6-gate MOSFET for freeze-out-free depletion-type MOSFET of high-speed E/D MOSLSI at low temperature. The work function of LaB_6 thin film was determined to be 3.5eV from C-V curves of LaB_6/SiO_2/p-Si MIS structure. The LaB_6-gate MOSFET fabricated using the self-align technique exhibited FET characteristics. Less

随着对高速、高密度的要求，超大规模集成电路的集成度也在逐年提高。应当注意，即使在目前，需要大功率耗散以用于高速操作的逻辑-VLSI的集成密度也受到芯片的热容量的限制。虽然基于约瑟夫森逻辑电路的低温电子学是一种高速、高密度的大规模集成电路，但我们注意到，基于硅超大规模集成电路技术的低温电子学是最有希望突破现有超大规模集成电路限制的候选者。本研究主要围绕以下几个方面展开：1.开发一种新的封装概念，其热容量比传统封装大一到两个数量级.提出了一种新的低温工作高速硅MOSFET的设计原理，并研制出低温工作的基本MOS器件。在本研究项目中，我们对冷电子 ...更多信息 1987-1990年进行了四年的ICS试验，取得了如下结果：1.我们提出了“一个微通道鳍封装”，利用氮化铝钝化层作为散热器内的芯片和微通道鳍作为有效的散热方法从芯片。新封装的热性能进行了评估，使用我们的模拟器的动态热分析在两个/三个维度。当使用水冷微通道翅片时，VLSI芯片中的耗散功率可以高达1.5kW/cm ^2。在1cm ~ 2的芯片上集成了500 k门以上的ECL电路，每门功率为3 mW。当压缩空气冷却微通道变细时，耗散功率允许高达30 W/cm ^2。微通道翅片封装的热容量比传统封装大一到两个数量级。2.我们提出了一个新的标度理论，“温度标度理论”，有关的操作温度。使用我们的器件模拟器在两个/三个维度，我们发现，电流-电压特性按比例缩小的操作温度，而移动载流子分布保持不变。根据温度定标理论，0.1 μ mMOSFET的最佳电源电压为1-1.5V，门延迟时间估计为1.6psec。在此基础上，我们研制了一种用于高速E/D MOSLSI的LaB_6栅无冻结耗尽型MOSFET。由LaB_6/SiO_2/p-Si MIS结构的C-V曲线确定LaB_6薄膜的功函数为3.5eV。采用自对准技术制备的LaB_6栅MOSFET具有FET特性。少