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A Study on Wide Bandwidth and Low Power Inductive-Coupling Inter-Chip Wireless Communication

宽带宽、低功耗电感耦合片间无线通信的研究

基本信息

批准号：
16206037
负责人：
KURODA Tadahiro
金额：
$ 30.7万
依托单位：
Keio University
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (A)
财政年份：
2004
资助国家：
日本
起止时间：
2004 至 2006
项目状态：
已结题

来源：
https://kaken.nii.ac.jp/en/grant/KAKENHI-PROJECT-16206037/
关键词：
LSI CMOS SiP low power interface wireless inter-chin communication inductive coupling

项目摘要

The computation speed shows an exponential improvement due to the improvement over speed and integration of transistor by scaling on LSI fabrication process. On the other hand, conventional LSI system by printing board implementation, the transmission rate of inter-chip is limited because of the distance and restriction of the number of 10 channels. As a result the performance gap between transmission rate of inter-chip and computation speed became expanded. Nowadays, inter-chip communication becomes main key factor which determines performance of overall LSI system. 3-D stacked implementation in LSI system is a hot topic as a technique which is expected to solve the issue. Stacked inter-chip inductive communication which is proposed in the study is a inter-chip wireless communication technology where inductive coupling between inductors mounted in chip is used as input-output channels. Establishment of the technology becomes the key to realize high performance LSI system. In the study … More , Design theory for minimizing area of inductive coupling channels is established and the technique to reduce crosstalk between the channels, an issue occurs when channels are arranged, is proposed. By utilizing the technology, design, fabrication and evaluation of test chip with channels arranged in high-density are held and realization for high-speed inter-chip communication became the purpose of the study. Array channels with mounted proposed circuit technology are designed. Test chip is fabricated and the performance is evaluated. 4-phase Time Division Multiple Access (TDMA) is realized by creating 4-phase clock from phase-interpolation circuits. Crosstalk can be reduced by occupying Time Division Multiple Access and channel array pitch can be reduced to 30 μ m. As a result, 1mm^2 area of array is achieved. By arranging 1024 inductive coupling channel, communication performance (BER <10^<-13>) and wide bandwidth (1Tb/s) are improved. By changing modulation scheme into Bi-phase modulation scheme and improving receiver's noise-tolerance, 2mW of reduction in transmission power is achieved. Less

计算速度显示出指数的提高，由于在速度和集成度的晶体管通过缩放上LSI制造工艺的改善。另一方面，常规LSI系统通过印刷板实现，芯片间的传输速率由于距离和10个通道的数量的限制而受到限制。其结果是，芯片间的传输速率和计算速度之间的性能差距变得扩大。目前，芯片间通信已成为决定整个LSI系统性能的主要关键因素。大规模集成电路系统中的三维堆叠实现是一个热门话题，作为一种技术，有望解决这个问题。本研究提出的堆叠式芯片间感应通信是一种利用芯片内电感之间的感应耦合作为输入输出通道的芯片间无线通信技术。该技术的建立成为实现高性能大规模集成电路系统的关键。研究中 ...更多信息建立了电感耦合通道面积最小化的设计理论，提出了减小通道间串扰的技术。利用该技术，进行了通道高密度排列的测试芯片的设计、制造和评估，实现了高速芯片间通信成为研究的目的。采用提出的电路技术设计了阵列通道。制作了测试芯片并进行了性能评估。4-相位时分多址（TDMA）是通过相位内插电路产生4相位时钟来实现的。采用时分多址接入方式可以减小串扰，信道阵列间距可以减小到30 μ m。结果，实现了1mm^2的阵列面积。通过布置1024个电感耦合通道，提高了通信性能（BER <10^<-13>）和宽带宽（1 Tb/s）。通过将调制方式改为双相调制方式，提高接收机的抗噪声能力，使发射功率降低了2 mW。少

项目成果

期刊论文数量（47）

专著数量（0）

科研奖励数量（0）

会议论文数量（0）

专利数量（0）

Measurement of Inductive Coupling in Wireless Superconnect

无线超级连接中的电感耦合测量

DOI：
发表时间：
2005
期刊：
International Conference on Solid State Devices and Materials (SSDM'05)
影响因子：
0
作者：
D.Mizoguchi;他
通讯作者：
他

Design of Transceiver Circuits for NRZ Signaling in Inductive Inter-chip Wireless Superconnect

感应式片间无线超级连接中 NRZ 信令收发器电路设计

DOI：
发表时间：
2005
期刊：
2005 International Conference on Integrated Circuit Design and Technology (ICICDT)
影响因子：
0
作者：
D.Mizoguchi;他
通讯作者：
他

Perspective of Low-Power and High-Speed Wireless Inter-Chip Communications for SiP Integration

SiP 集成的低功耗高速无线片间通信前景

DOI：
发表时间：
2006
期刊：
European Solid-State Circuits Conference
影响因子：
0
作者：
T.Eki;S.Kawahito;Y.Tadokoro;T.Kuroda 他
通讯作者：
T.Kuroda 他

Non-Contact Inter-Chip Data Communications Technology for System in a Package

系统级封装非接触式片间数据通信技术

DOI：
发表时间：
2004
期刊：
Proc. of IEEE International Conference on Solid-State and Integrated Circuits Technology (ICSICT' 04)
影响因子：
0
作者：
K. Kajikawa;K. Tomachi;N. Maema;M. Matsuo;S. Sato;K. Funaki;H. Kumakura;K. Tanaka;M. Okada;K. Nakamichi;Y. Kihara;T. Kamiya;I. Aoki;T.Kuroda
通讯作者：
T.Kuroda

Power Reduction in High-Speed Inter-Chip Data Communications

高速芯片间数据通信的功耗降低