Implementation of a High-Speed Asynchronous Data Transfer VLSI Based on Bidirectional Current-Mode Multiple-Valued Circuit Techniques

在最近的深亚微米VLSI中，时钟分布等全球互连延迟的趋势正在成为一个重要的问题。随着cmos技术从一代到下一代的发展，互连电阻和负载电容的乘积并没有随着技术的发展而升级。解决上述互连问题的可能方法之一是使用异步电路实现。双轨编码被广泛用作异步数据传输的一种编码风格，其中每个逻辑变量都使用两条线进行编码，并且时序信息也隐含在代码中。每个异步数据传输协议都基于请求-确认握手：每个传输的特点是发起方开始传输的请求动作和允许目标作出响应的确认动作。这样，信号在发送器和接收器之间往返传播，从而数据传输的周期变得很长，这是…所伴随的问题本质上是更多的NG异步数据传输。如果同时执行上述步骤，则采用双轨编码的异步数据传输的周期时间变得比传统方法快得多。在这项研究中，提出了一种新的异步数据传输协议，称为双色“1-pbase”双轨编码，用于高速异步数据传输。双色一相编码有两种颜色，分别表示奇数和偶数两种数据定义，通过交替传输不同颜色的码字来检测不同的有效数据。在该协议中，接收器和发送器都将颜色信息作为请求信号发送，然后通过检测相互的颜色信息是否相同来进行数据传输。因为两个请求信号可以同时发送，所以可以进行重叠通信。由于在异步数据传输中，数据和颜色信息必须捆绑在同一导线上，因此从数据和颜色信息的混合双轨代码中检测有效数据是很重要的。所提出的编码的使用使得通过计算码字的和来合并和检测数据和颜色信息变得容易。在多值双向电流模式电路中，由于不需要任何有源器件就可以通过布线实现电流模式线性求和，因此所提出的异步电路变得简单。此外，来自两侧的电流信号可以叠加在同一根导线上，这是多值电流模式逻辑实现控制信号多路复用的重要特性。比较器和读出放大器的使用使得快速检测码字的分量和变得容易。事实上，在0.18um的CMOS工艺下，使用多值电流模式逻辑电路的异步数据传输方案的数据传输周期在归一化功耗下比相应的二值CMOS实现快约1.5倍。较少

The trend in global interconnection delay such as clock distribution is becoming a significant problem in recent deep submicron VLSI. As CMOS technology scales from one generation to the next, the product of the interconnect resistance and load capacitance is not scaling with technology. One of the possible methods to solve the above interconnection problems is to use asynchronous circuit implementation. Dual-rail encoding is widely used as an encoding style of asynchronous data transfer, where every logical variable is encoded using two wires and timing information is also implicit in the code. Every asynchronous data transfer protocol is based on request-acknowledge handshaking : every transfer features a request action where the initiator starts a transfer, and an acknowledge action allowing the target to respond. In this way, the signals propagate round trip between the transmitter and the receiver, thus the cycle time of data transfer becomes large, which is the problem accompanyi … More ng asynchronous data transfer essentially. If the above procedures are executed simultaneously, the cycle time of the asynchronous data transfer with dual-rail encoding becomes much faster than that of the conventional methods. In this research, a new asynchronous data-transfer protocol, called 2-color "1-pbase" dual-rail encoding, is proposed for high-speed asynchronous data transfer. The 2-color 1-phase encoding has two colors which mean two kinds of data definition "ODD" and "EVEN", and different valid data is detected by transferring codewords which have different color alternately. In this protocol, the receiver as well as the transmitter sends the color information as the request signal, then the data transfer is performed by detecting whether the mutual color information is same or not. Because the both request signals can be sent simultaneously, overlap communication can be done. Since data and color information must be bundled on the same wires in the asynchronous data transfer, it is important to detect valid data from the mixed dual-rail code of data and color information. The use of the proposed encoding makes it easy to merge and detect data and color information by calculating the sum of the codewords. In multiple-valued bidirectional current-mode circuits, since current-mode linear summation can be implemented by wiring without any active devices, the proposed asynchronous circuit becomes simple. Moreover, current signals from both sides can be superposed on the same wires, which is an important characteristic of multiple-valued current-mode logic to realize a control signal multiplexing scheme. The use of comparators with sense amplifier makes it easy to detect the sum of components of the codewords quickly. In fact, it is evaluated in a 0.18um CMOS technology that the data transfer cycle of the proposed asynchronous data-transfer scheme using the multiple-valued current-mode logic circuit is about 1.5-times faster than that of the corresponding binary CMOS implementation under the normalized power dissipation. Less