Implementation of a High-Performance Multiple-Valued Current-Mode VLSI System with Low-Power and Highly Reliable Capabilities

在保持高速性能的同时，低功耗电路设计不仅需要电池供电的便携式应用，而且还需要减少专用专用VLSI处理器的功耗，因为互连中的额外电流密度会导致电压下降或电迁移导致暂时或永久故障。多值电流模式（MVCM）集成电路在算术大规模集成芯片中具有降低布线复杂性和减少有源器件数量的潜在优势，因为经常使用的线性和运算可以简单地通过不带有源器件的布线来完成。然而，MVCM电路的开关速度相对较慢，并且由于差分对电路中的电流源在有源模式下始终以恒定电流流过，因此由稳态电流引起的功耗变得很高。在这个项目中，我们提出了一种新的基于双轨差分逻辑的MVCM电路，用于高速、低功耗、高可靠的面向算法的VLSI。差分逻辑电路有一个吸引人的特点，它的输入电压摆幅足够小，同时保持高电流驱动能力。在算术VLSI中，差分逻辑风格与MVCM电路的结合使得与相应的二进制CMOS实现相比，可以提高开关速度。此外，采用预充评估的逻辑方式，使稳定电流切断，从而大大降低了动态功耗。在所提出的电路中，差分逻辑、MVCM逻辑和动态逻辑的明智组合使得在保持高速交换能力的同时减少功耗、器件和互连计数成为可能。双轨编码是一种广泛应用于异步和自检电路实现的编码方式，应用于差分逻辑电路。从这个角度来看，我们还提出了使用多值双轨互补信号的高性能异步自检电路。少

Low-power circuit design while maintaining a high-speed capability is needed not only for battery-powered portable applications but also to reduce the power dissipation of dedicated apecial-purpose VLSI processors, because the extra current density in interconnections causes temporal or permanent malfunction due to voltage drops or electromigrations. Multiple-valued current-mode (MVCM) integrated circuits have a potential advantage to reduce the wiring complexity and the nurnber of active devices in arithmetic large-scale-integration chips because the frequently used linear sum operation can be performed simply by wiring with no active devices. However, the switching speed in the MVCM circuit is relatively slow, and its power dissipation due to the steady current becomes high because current-sources in differential-pair circuits always flow a constant current in the active mode. In this project, a new MVCM circuit based on dual-rail differential logic has been proposed for high-speed, … More low-power, highly reliable arithmetic-oriented VLSI. A differential logic-style circuit has an attractive feature that its input voltage swing is small enough while maintaining a high currentdriving capability. The combination of the differential logic style and MVCM circuitry in arithmetic VLSI makes it possible to improve the switching speed compared with that of a corresponding binary CMOS implementation. Moreover, the use of a precharge-evaluate logic style abo makes the steady current flow cut off, which results in great reduction of dynamic power dissipation. A judicious combination of differential logic, MVCM logic and dynamic logic in the proposed circuit makes it possible to reduce the power dissipation together with device and interconnection counts while maintaining a high-speed switching capability. The use of dual-rail coding, which is used in differential logic-style circuit, is a widely used encoding style of asynchronous and self-checking circuit implementation. From this point of view, we have also proposed high-performance asynchronous and self-checking circuit using multiple-valued dual-rail complementary signals. Less