Implementation of a High-Performance Multiple-Valued Current-Mode VLSI System with Low-Power and Highly Reliable Capabilities

低功耗电路设计，同时保持一个高速的能力，不仅需要为电池供电的便携式应用，而且还需要减少专用ape-purpose VLSI处理器的功耗，因为额外的电流密度互连导致暂时或永久故障，由于电压降或电迁移。多值电流模式（MVCM）集成电路在算术大规模集成电路中具有降低布线复杂度和减少有源器件数量的潜在优势，因为它可以通过简单的布线而无需有源器件来完成经常使用的线性和运算。然而，MVCM电路中的开关速度相对较慢，并且由于差分对电路中的电流源在有源模式下总是流动恒定电流，因此由于稳定电流而导致的功耗变高。在本计画中，提出一种新的基于双轨差动逻辑的MVCM电路， ...更多信息 低功耗、高可靠性的面向运算的VLSI。差分逻辑型电路具有输入电压摆幅足够小而又能保持高电流驱动能力的特点。在算术VLSI中，差分逻辑风格和MVCM电路的结合使得与相应的二进制CMOS实现相比，可以提高开关速度。此外，使用了一种预充电评估逻辑的方式，使稳定的电流流动切断，这导致了动态功耗大大降低。差分逻辑，MVCM逻辑和动态逻辑在建议的电路中的明智的组合，使它能够降低功耗连同设备和互连计数，同时保持高速开关能力。双轨编码的使用，是一种广泛应用于差分逻辑式电路的异步和自校验电路实现的编码方式。从这个角度出发，我们还提出了使用多值双轨互补信号的高性能异步自检电路。少

Low-power circuit design while maintaining a high-speed capability is needed not only for battery-powered portable applications but also to reduce the power dissipation of dedicated apecial-purpose VLSI processors, because the extra current density in interconnections causes temporal or permanent malfunction due to voltage drops or electromigrations. Multiple-valued current-mode (MVCM) integrated circuits have a potential advantage to reduce the wiring complexity and the nurnber of active devices in arithmetic large-scale-integration chips because the frequently used linear sum operation can be performed simply by wiring with no active devices. However, the switching speed in the MVCM circuit is relatively slow, and its power dissipation due to the steady current becomes high because current-sources in differential-pair circuits always flow a constant current in the active mode. In this project, a new MVCM circuit based on dual-rail differential logic has been proposed for high-speed, … More low-power, highly reliable arithmetic-oriented VLSI. A differential logic-style circuit has an attractive feature that its input voltage swing is small enough while maintaining a high currentdriving capability. The combination of the differential logic style and MVCM circuitry in arithmetic VLSI makes it possible to improve the switching speed compared with that of a corresponding binary CMOS implementation. Moreover, the use of a precharge-evaluate logic style abo makes the steady current flow cut off, which results in great reduction of dynamic power dissipation. A judicious combination of differential logic, MVCM logic and dynamic logic in the proposed circuit makes it possible to reduce the power dissipation together with device and interconnection counts while maintaining a high-speed switching capability. The use of dual-rail coding, which is used in differential logic-style circuit, is a widely used encoding style of asynchronous and self-checking circuit implementation. From this point of view, we have also proposed high-performance asynchronous and self-checking circuit using multiple-valued dual-rail complementary signals. Less