权益分类	功能权益	普通用户	{{item.name}}会员
{{category.name}}	{{benefitItem.name}}

Implementation of a One-Transistor Multiple-Valued Content-Addressalbe Memory and Its Application

一种单晶体管多值内容寻址存储器的实现及其应用

基本信息

批准号：
09558027
负责人：
HANYU Takahiro
金额：
$ 7.49万
依托单位：
Tohoku Univesity
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (B).
财政年份：
1997
资助国家：
日本
起止时间：
1997 至 2000
项目状态：
已结题

项目摘要

Communication bottleneck between memory and logic modules is one of the most serious problems in the multimedia VLSI systems on a chip. A logic-in-memory structure, in which logic-circuit elements are distributed over a memory-cell array, is a key technology to solve the above problem. A content-addressable memory (CAM) is one of the typical logic-in-memory VLSIs. However, CAMs have been more complex to build and had lower storage density than a normal memory such as RAMs because of the overhead involved in the storage and logic elements.In this project, a high-performance multiple-valued CAM based on floating-gate-MOS pass-transistor logic is proposed to perform highly parallel magnitude comparisons in a limited chip area. Multiple-valued stored data in the proposed CAM correspond to the threshold voltage of a floating-gate MOS transistor, so that the CAM cell circuit can be designed by using only a single MOS transistor. Moreover, a logic-in-memory VLSI architecture based on such a multiple-valued floating-gate-MOS pass-transistor network is also proposed to realize parallel arithmetic and logic circuits with multiple-valued inputs and binary outputs. The main results of this project are listed below :(1) Highly Parallel Magnitude-Comparison Hardware Algorithm for CAMs,(2) Logic-in-Memory VLSI Architecture Using Floating-Gate MOS-Based Multiple-Valued Pass-Transistor Network,(3) Functional Pass Gate Based on Ferroelectric Devices and Their Application,(4) Current/Voltage-Hybrid-Mode Multiple-Valued Integrated Circuits.

存储器与逻辑模块之间的通信瓶颈是多媒体集成电路片上系统中最严重的问题之一。其中逻辑电路元件分布在存储单元阵列上的存储器中逻辑结构是解决上述问题的关键技术。内容可寻址存储器（CAM）是一种典型的存储器中逻辑超大规模集成电路。然而，CAM一直是更复杂的建设，并有较低的存储密度比普通的存储器，如RAM，因为在存储和逻辑元件的开销，在这个项目中，提出了一个高性能的多值CAM浮栅MOS传输晶体管逻辑的基础上，在有限的芯片面积进行高度并行的幅度比较。该CAM中的多值存储数据对应于浮栅MOS晶体管的阈值电压，因此CAM单元电路可以仅使用单个MOS晶体管来设计。此外，还提出了一种基于这种多值浮栅MOS传输晶体管网络的逻辑存储器VLSI结构，以实现具有多值输入和二进制输出的并行算术和逻辑电路。本计画之主要成果包括：（1）高度平行化之CAM之类比量硬体演算法，（2）以浮闸MOS为基础之多值传输电晶体网路之逻辑记忆体超大型积体电路架构，（3）以铁电元件为基础之功能传输门及其应用，（4）电流/电压混合模式之多值积体电路。