Implementation of a One-Transistor Multiple-Valued Content-Addressalbe Memory and Its Application
Implementation of a One-Transistor Multiple-Valued Content-Addressalbe Memory and Its Application
批准号:
09558027
负责人:
HANYU Takahiro
金额:
$7.49万
依托单位:
依托单位国家:
日本
项目类别:
Grant-in-Aid for Scientific Research (B).
财政年份:
1997
资助国家:
日本
项目状态:
已结题
起止时间:
1997 至 2000
中文摘要
存储模块和逻辑模块之间的通信瓶颈是多媒体VLSI系统中最严重的问题之一。其中逻辑电路元件分布在存储单元阵列上的存储器中逻辑结构是解决上述问题的关键技术。内容可寻址存储器(CAM)是典型的存储器中逻辑超大规模集成电路的一种。然而,由于存储和逻辑元素的开销,CAM的构建更加复杂,存储密度也低于RAM等常规存储器,因此提出了一种基于浮栅MOS传输管逻辑的高性能多值CAM,用于在有限的芯片面积内执行高度并行的幅度比较。所提出的多值存储数据对应于浮栅MOS晶体管的阈值电压,因此可以仅使用单个MOS晶体管来设计CAM单元电路。此外,还提出了一种基于这种多值浮栅MOS传递晶体管网络的存储器中逻辑VLSI结构,以实现具有多值输入和二进制输出的并行算术和逻辑电路。本项目的主要成果如下:(1)凸轮高度并行的幅度比较硬件算法;(2)基于浮栅MOS的多值通道晶体管网络的存储器中逻辑VLSI结构;(3)基于铁电器件的功能通道门及其应用;(4)电流/电压混合模式多值集成电路。
英文摘要
Communication bottleneck between memory and logic modules is one of the most serious problems in the multimedia VLSI systems on a chip. A logic-in-memory structure, in which logic-circuit elements are distributed over a memory-cell array, is a key technology to solve the above problem. A content-addressable memory (CAM) is one of the typical logic-in-memory VLSIs. However, CAMs have been more complex to build and had lower storage density than a normal memory such as RAMs because of the overhead involved in the storage and logic elements.In this project, a high-performance multiple-valued CAM based on floating-gate-MOS pass-transistor logic is proposed to perform highly parallel magnitude comparisons in a limited chip area. Multiple-valued stored data in the proposed CAM correspond to the threshold voltage of a floating-gate MOS transistor, so that the CAM cell circuit can be designed by using only a single MOS transistor. Moreover, a logic-in-memory VLSI architecture based on such a multiple-valued floating-gate-MOS pass-transistor network is also proposed to realize parallel arithmetic and logic circuits with multiple-valued inputs and binary outputs. The main results of this project are listed below :(1) Highly Parallel Magnitude-Comparison Hardware Algorithm for CAMs,(2) Logic-in-Memory VLSI Architecture Using Floating-Gate MOS-Based Multiple-Valued Pass-Transistor Network,(3) Functional Pass Gate Based on Ferroelectric Devices and Their Application,(4) Current/Voltage-Hybrid-Mode Multiple-Valued Integrated Circuits.
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T.Hanyu: "Design and Evaluation of a 4-Valued Universal-Literal CAM for Cellular Logic Image Processing"IEICE Trans.Electronics. E80-C・7. 948-955 (1997)
T.Hanyu:“用于细胞逻辑图像处理的 4 值通用文字 CAM 的设计和评估”IEICE Trans.Electronics。 948-955。
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羽生貴弘: "2色2線式電流モード多値非同期VLSIシステムとその応用"電子情報通信学会技術研究報告. 100・30. 9-15 (2000)
Takahiro Hanyu:“双色两线电流模式多级异步VLSI系统及其应用”IEICE技术报告100・30(2000)。
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T.Hanyu: "Multiple-Valued Logic-in-Memory VLSI and Its Application"International Workshop on Post-Binary ULSI.
T.Hanyu:“多值逻辑内存VLSI及其应用”后二进制ULSI国际研讨会。
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T.Hanyu: "Multiple-Valued Mask-Programmable Logic Array Using One-Transistor Universal-Literal Circuits"Proc.of 31^<st> IEEE International Symposium on Multiple-valued Logic. (to be published). (2001)
T.Hanyu:“使用单晶体管通用文字电路的多值掩模可编程逻辑阵列”Proc.of 31^<st> IEEE 国际多值逻辑研讨会。
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T.Hanyu and M.Kameyama: "Universal-Literal-Type Multiple-Valued Logic Array Using Floating-Gate MOS Transistors""Note on Multiple-Valued Logic in Japan. Vol.21, No.12. 12-1-12-9 (1998)
T.Hanyu 和 M.Kameyama:“使用浮栅 MOS 晶体管的通用文字型多值逻辑阵列”“日本多值逻辑注释。第 21 卷,第 12 期。12-1-12-
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共 95 条
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Implementation of a Transfer-Bottleneck-Free Multiple-Valued Logic-in-Memory VLSI and Its Application
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资助金额:$8.7万
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财政年份:2001
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依托单位:
Implementation of a High-Performance Multiple-Valued Current-Mode VLSI System with Low-Power and Highly Reliable Capabilities
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批准号:12680324
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项目类别:Grant-in-Aid for Scientific Research (C)
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资助金额:$2.37万
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财政年份:2000
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负责人:HANYU Takahiro
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依托单位:
MULTIPLE-VALUED PROCESSOR FOR INTELLIGENT INTEGRATED SYSTEM
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批准号:09044125
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项目类别:Grant-in-Aid for international Scientific Research
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资助金额:$1.98万
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财政年份:1997
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负责人:HANYU Takahiro
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依托单位: