HYPNOS - Co-Design of Persistent, Energy-efficient and High-speed Embedded Processor Systems with Hybrid Volatility Memory Organisation

Project Hypnos探讨了新兴的非易失性存储器(NVM)技术如何不仅可以有益地取代现代嵌入式处理器体系结构中的主存储器，还可以潜在地取代一级或多级高速缓存层次结构甚至寄存器，以及如何优化这种混合易失性存储器层次结构，以便为大量应用程序提供高速和低能耗的折衷，同时以简单有效的方式提供数据结构和处理状态的持久性。一方面，已为物联网设备出现的完全非易失性(存储器)处理器(NVP)已知遭受当前NVM技术的低写入时间以及比例如SRAM低数量级的耐久性，从而禁止以GHz速度进行操作。另一方面，现有的NVM主存储器计算机解决方案需要程序员显式地在高速缓存分层结构中持久存储数据结构。Hypnos(以希腊睡神命名)通过采取硬件/软件联合设计的方法系统地攻击这种相互交织的性能/耐力/可编程性差距：我们的研究包括a)设计空间探索混合NVM内存处理器架构的技术}WRT。包括混合(混合易失性)寄存器和高速缓存级设计的速度和能量消耗，b)通过检查点和恢复功能的低成本和低等待时间控制单元(硬件)设计，在例如瞬时电源故障的情况下为(非事务性)程序提供指令级持久性，D)所探索的处理器体系结构设计和不同类型的NVM技术将被系统地评估以获得可实现的速度和能量增益，并用于测试共同设计的备份和恢复机制，例如唤醒等待时间等。Ii)传感器(外围设备)I/O，最后是iii)事务数据库应用程序应进行协作调查和评估。

Project HYPNOS explores how emerging non-volatile memory (NVM) technologies could beneficially replace not only main memory in modern embedded processor architectures, but potentially also one or multiple levels of the cache hierarchy or even the registers and how to optimize such a hybrid-volatile memory hierarchy for offering high speed and low energy tradeoffs for a multitude of application programs while providing persistence of data structures and processing state in a simple and efficient way. On the one hand, completely non-volatile (memory) processors (NVPs) that have emerged for IoT devices are known to suffer from low write times of current NVM technologies as well as by orders of magnitude lower endurance than, e.g., SRAM, thus prohibiting an operation at GHz speeds. On the other hand, existing NVM main memory computer solutions suffer from the need of the programmer to explicitly persist data structures through the cache hierarchy. HYPNOS (Named after the Greek god of sleep) systematically attacks this intertwined performance/endurance/programmability gap by taking a hardware/software co-design approach:Our investigations include techniques fora) design space exploration of hybrid NVM memory processor architectures} wrt. speed and energy consumption including hybrid (mixed volatile) register and cache-level designs,b) offering instruction-level persistence for (non-transactional) programs in case of, e.g., instantaneous power failures through low-cost and low-latency control unit (hardware) design of checkpointing and recovery functions, and additionally providingc) application-programmer (software) persistence control on a multi-core HyPNOS system for user-defined checkpointing and recovery from these and other errors or access conflicts backed by size-limited hardware transactional memory (HTM).d) The explored processor architecture designs and different types of NVM technologies will be systematically evaluated for achievable speed and energy gains, and for testing co-designed backup and recovery mechanisms, e.g., wakeup latencies, etc., using a gem5-based multi-core simulation platform and using ARM processors with HTM instruction extensions.As benchmarks, the hierarchyfrom i) simple data structures, ii) sensor (peripheral device) I/O and finally iii) transactional database applications shall be collaboratively investigated and evaluated.