HYPNOS - Co-Design of Persistent, Energy-efficient and High-speed Embedded Processor Systems with Hybrid Volatility Memory Organisation

HYPNOS - 持久、节能和高速嵌入式处理器系统与混合易失性内存组织的联合设计

• 批准号: 502213043
• 负责人: Professor Dr.-Ing. Jürgen Teich
• 金额: --
• 依托单位: Lehrstuhl für Informatik 6: Datenmanagement
• 依托单位国家: 德国
• 项目类别: Priority Programmes
• 资助国家: 德国
• 项目状态: 未结题
• 来源: https://gepris.dfg.de/gepris/projekt/502213043?language=en
• 关键词: HYPNOS; Co; Design; Persistent; Energy

Project HYPNOS explores how emerging non-volatile memory (NVM) technologies could beneficially replace not only main memory in modern embedded processor architectures, but potentially also one or multiple levels of the cache hierarchy or even the registers and how to optimize such a hybrid-volatile memory hierarchy for offering high speed and low energy tradeoffs for a multitude of application programs while providing persistence of data structures and processing state in a simple and efficient way. On the one hand, completely non-volatile (memory) processors (NVPs) that have emerged for IoT devices are known to suffer from low write times of current NVM technologies as well as by orders of magnitude lower endurance than, e.g., SRAM, thus prohibiting an operation at GHz speeds. On the other hand, existing NVM main memory computer solutions suffer from the need of the programmer to explicitly persist data structures through the cache hierarchy. HYPNOS (Named after the Greek god of sleep) systematically attacks this intertwined performance/endurance/programmability gap by taking a hardware/software co-design approach:Our investigations include techniques fora) design space exploration of hybrid NVM memory processor architectures} wrt. speed and energy consumption including hybrid (mixed volatile) register and cache-level designs,b) offering instruction-level persistence for (non-transactional) programs in case of, e.g., instantaneous power failures through low-cost and low-latency control unit (hardware) design of checkpointing and recovery functions, and additionally providingc) application-programmer (software) persistence control on a multi-core HyPNOS system for user-defined checkpointing and recovery from these and other errors or access conflicts backed by size-limited hardware transactional memory (HTM).d) The explored processor architecture designs and different types of NVM technologies will be systematically evaluated for achievable speed and energy gains, and for testing co-designed backup and recovery mechanisms, e.g., wakeup latencies, etc., using a gem5-based multi-core simulation platform and using ARM processors with HTM instruction extensions.As benchmarks, the hierarchyfrom i) simple data structures, ii) sensor (peripheral device) I/O and finally iii) transactional database applications shall be collaboratively investigated and evaluated.

HYPNOS项目探讨了新兴的非易失性存储器（NVM）技术如何不仅可以有益地取代现代嵌入式处理器架构中的主存储器，而且潜在地还包括该高速缓存层次结构的一个或多个级别或者甚至寄存器，以及如何优化这种混合-易失性存储器层次结构，用于为大量应用程序提供高速和低能量折衷，同时提供数据结构和处理的持久性以一种简单而有效的方式。 一方面，已经出现的用于IoT设备的完全非易失性（存储器）处理器（NVP）已知遭受当前NVM技术的低写入时间以及比例如SRAM，从而禁止以GHz速度操作。另一方面，现有的NVM主存储器计算机解决方案受到程序员需要通过该高速缓存层级显式地保持数据结构的困扰。 HYPNOS（以希腊睡眠之神命名）通过采用硬件/软件协同设计方法系统地解决了这种交织在一起的性能/耐久性/可编程性差距：我们的研究包括混合NVM存储器处理器架构的设计空间探索技术。速度和能量消耗，包括混合（混合易失性）寄存器和高速缓存级设计，B）在例如，通过低成本和低延迟控制单元的瞬时电源故障检查点和恢复功能的（硬件）设计，并另外提供c）应用程序员d）多核HyPNOS系统上的（软件）持久性控制，用于用户定义的检查点设置和从这些和其他错误或由大小受限的硬件事务存储器（HTM）支持的访问冲突中恢复。将系统地评估所探索的处理器架构设计和不同类型的NVM技术，以实现速度和能量增益，并测试共同设计的备份和恢复机制，例如，唤醒延迟等，使用基于gem 5的多核仿真平台和使用具有HTM指令扩展的ARM处理器。作为基准，应协同调查和评估i）简单数据结构，ii）传感器（外围设备）I/O和iii）事务数据库应用程序的层次结构。