HIGH SPEED PARALLEL COMPUTER SYSTEM USING 3-DIMENTIONAL INTEGLATED SHARED MEMORY

使用3维集成共享存储器的高速并行计算机系统

• 批准号: 08505003
• 负责人: KOYANAGI Mitsumasa
• 金额: $ 24.06万
• 依托单位: TOHOKU UNIVERSITY
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for Scientific Research (A)
• 财政年份: 1996
• 资助国家: 日本
• 起止时间: 1996 至 1998
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-08505003/
• 关键词: Three Dimensional Integration Technology; Three Dimensional Integrated Shard Memory; High Speed parallel Computing System; Bus Bottle Neck; Parallel Monte Carlo Analysis; Device Simulation; Deca-nano device; ULSI

This project aimed to develop a compact parallel computer system specific for the Monte-Carlo simulation. The results are summarized as follows :1. Parallel computer system specific for the Monte-Carlo simulation. System ana1ysis of the first version parallel computer was completed on 1997. The second version has been designed since 1997. In second version, the communication bus and protocol are dramatically improved for speeding up the inter-processor communication. A new ring bus pipe line architecture is proposed and is introduced into the second version design. The data coming through the ring bus are processed at each processing unit in parallel and sent to next processing unit. Therefore, a combined system of ring bus and processing units act as a huge pipe line. The architecture level design has been completed.2. Three dimensional integration technologyThe following three key technologies have been developed for three-dimensional integrated circuit.(a) Micro-bump formationA new … More lift-off technology has been developed for the micro-bump formation. Indium(In)-gold(Au) micro-bumps as small as 5 mu m can be easily formed by using this technology. It was found that thin tungsten film inserted between In-Au micro-bump and aluminum electrode is very effective to reduce the contact resistance. A very low contact resistance of 0.05 OMEGA per micro-bump was obtained.(b) Wafer alignment and bondingSeveral wafers are stacked and bonded for three -dimensional integration after careful wafer alignment. A new vacuum adhesive injection method was developed for gluing the wafers. Liquid adhesive was injected into the small gap between two stacked wafers in vacuum ambient applying a mechanical pressure from both sides of wafers. Injected liquid adhesive was cured at 180ﾟC.This procesure improved the bondability of wafers and the electrical characteristics of micro-bumps.(c) Vertical interconnection and wafer thinningThe deep trench with the diameter of 3 mu m and the depth of 60 mum has been formed on a silicon substrate after optimizing the ICP(Inductively Coupled Plasma) etching condition. After the trench etching, oxidation, poly-silicon deposition, impurity diffusion and etching back of poly-silicon by CMP were performed. Thus, a low resistive vertical interconnection for three-dimensional integrated circuit has been successfully formed. Less

该项目旨在开发一个专用于蒙特-卡罗模拟的紧凑型并行计算机系统。主要研究结果如下：1.专用于蒙特-卡罗模拟的并行计算机系统。1997年完成了第一版并行计算机的系统分析。第二个版本自1997年以来一直在设计。在第二个版本中，通信总线和协议显着改进，以加快处理器间的通信。提出了一种新的环形总线管线结构，并将其引入到第二版设计中。通过环形总线的数据在每个处理单元并行处理并发送到下一个处理单元。因此，环形总线和处理单元的组合系统充当巨大的管线。完成了系统的体系结构设计.三维集成技术三维集成电路发展了以下三项关键技术。(a)微凸点形成新技术 ...更多信息 已经开发了用于微凸块形成的剥离技术。通过使用该技术可以容易地形成小至5 μ m的铟（In）-金（Au）微凸点。结果表明，在In-Au微凸点与铝电极之间插入钨薄膜可以有效地降低接触电阻。获得了每个微凸点0.05 Ω的非常低的接触电阻。(b)晶圆对准和键合在仔细的晶圆对准后，将几个晶圆堆叠并键合，以实现三维集成。提出了一种新的真空注胶方法。在真空环境中，从晶片的两侧施加机械压力，将液体粘合剂注入两个堆叠晶片之间的小间隙中。注入的液态胶在180 ℃下固化，改善了晶片的可键合性和微凸点的电学特性。(c)垂直互连和晶片减薄通过优化ICP（电感耦合等离子体）刻蚀条件，在硅衬底上形成了直径为3 μ m、深度为60 μ m的深沟槽。在沟槽蚀刻之后，进行氧化、多晶硅沉积、杂质扩散和通过CMP对多晶硅的回蚀刻。因此，已成功地形成用于三维集成电路的低电阻垂直互连。少

项目成果

K.Sakuma,M.Koyanagi,et.al: "A New Wafer-Scale Chip-on-Chip(W-COC)Packaging Technology Using Adhesive Injection Method" Extended Abstracts of the 1998 Conference on Solid State Devices and Materials. 286-287 (1998)

K.Sakuma、M.Koyanagi 等人：“采用粘合剂注入方法的新型晶圆级片上芯片 (W-COC) 封装技术”1998 年固态器件和材料会议的扩展摘要。

H.Kurino T.Matsumoto M.Koyanagi 他4人: "Three-Dimensional Integration Technology for Real Time Micro-Vision System" Proc.of the Intern. Conf.on Innovative Systems in Silicon. 203-212 (1997)

H.Kurino T.Matsumoto M.Koyanagi 等 4 人：“实时微视觉系统的三维集成技术”Proc.of the Intern. on Innovative Systems in Silicon（硅创新系统）。

T.Matsumoto H.Kurino M.Koyanagi 他2人: "Polyimide Optical Waveguide with Multi-Fan-Out for Multichip Module System" Proc.SPIE Int.Symp.on Optoelectronic, Microelectronic and Laser Technologies,. 3288. 133-144 (1998)

T.Matsumoto H.Kurino M.Koyanagi 等 2 人：“用于多芯片模块系统的多扇出聚酰亚胺光波导”Proc.SPIE Int.Symp.on 光电、微电子和激光技术，. 3288. 133-144 ( 1998）

D.Kawae H.Kurino M.Koyanagi: "Design of Real Time Micro-Vision System LSI with Three-Dimensional Structure" Proceedings.of the Workshop on Synthesis And System Integration of Mixed Technologies. 229-234 (1998)

D.Kawae H.Kurino M.Koyanagi：“具有三维结构的实时微视觉系统LSI的设计”混合技术综合与系统集成研讨会论文集。

T.Matsumoto Y.Noguchi Y.Kudoh M.Koyanagi: "Polyimide Optical Waveguide with Multi-Fan-Out for Multi-Chip Module Application" Jpn.J.Appl.Phys.Vol.36 Part 1, No.3B. 1903-1906 (1997)

T.Matsumoto Y.Noguchi Y.Kudoh M.Koyanagi：“用于多芯片模块应用的具有多扇出的聚酰亚胺光波导”Jpn.J.Appl.Phys.Vol.36 第 1 部分，No.3B。