HIGH SPEED PARALLEL COMPUTER SYSTEM USING 3-DIMENTIONAL INTEGLATED SHARED MEMORY

本项目旨在开发一个专门用于蒙特卡罗模拟的紧凑型并行计算机系统。研究结果总结如下：1.专门用于蒙特卡罗模拟的并行计算机系统。第一代并行机的系统分析于1997年完成。第二个版本自1997年以来一直在设计。在第二版中，为了加快处理器间的通信速度，对通信总线和协议进行了显著的改进。提出了一种新的环形母线管路体系结构，并将其引入到第二版设计中。每个处理单元并行处理来自环形总线的数据，并将其发送到下一个处理单元。因此，环形母线和处理单元的组合系统就像一条巨大的管道。已经完成了体系结构层的设计。三维集成技术为三维集成电路开发了以下三项关键技术。(A)微凸点形成一种新的…针对微凸体的形成，已经开发了更多的提离技术。利用这种技术可以很容易地形成小到5微米的铟(In)-金(Au)微凸点。研究发现，在In-Au微凸点和铝电极之间插入一层薄的钨薄膜可以有效地降低接触电阻。获得了非常低的接触电阻，每微凸点0.05omega。(B)晶片对准和键合经过仔细的晶片对准后，几个晶片被堆叠和键合，以实现三维集成。开发了一种新的真空粘结剂注射方法来粘合硅片。在真空环境中，将液体粘合剂注入两层晶片之间的小缝隙中，从晶片的两侧施加机械压力。注入的液体胶粘剂在180ﾟC下固化。该工艺改善了晶片的键合性和微凸点的电学特性。(C)垂直互连和晶片减薄优化了电感耦合等离子体刻蚀条件后，在硅衬底上形成了直径为3微米、深度为60微米的深槽。对多晶硅进行了刻蚀、氧化、多晶硅沉积、杂质扩散和多晶硅化学机械抛光后的背面刻蚀。从而成功地形成了一种用于三维集成电路的低阻垂直互连。较少

This project aimed to develop a compact parallel computer system specific for the Monte-Carlo simulation. The results are summarized as follows :1. Parallel computer system specific for the Monte-Carlo simulation. System ana1ysis of the first version parallel computer was completed on 1997. The second version has been designed since 1997. In second version, the communication bus and protocol are dramatically improved for speeding up the inter-processor communication. A new ring bus pipe line architecture is proposed and is introduced into the second version design. The data coming through the ring bus are processed at each processing unit in parallel and sent to next processing unit. Therefore, a combined system of ring bus and processing units act as a huge pipe line. The architecture level design has been completed.2. Three dimensional integration technologyThe following three key technologies have been developed for three-dimensional integrated circuit.(a) Micro-bump formationA new … More lift-off technology has been developed for the micro-bump formation. Indium(In)-gold(Au) micro-bumps as small as 5 mu m can be easily formed by using this technology. It was found that thin tungsten film inserted between In-Au micro-bump and aluminum electrode is very effective to reduce the contact resistance. A very low contact resistance of 0.05 OMEGA per micro-bump was obtained.(b) Wafer alignment and bondingSeveral wafers are stacked and bonded for three -dimensional integration after careful wafer alignment. A new vacuum adhesive injection method was developed for gluing the wafers. Liquid adhesive was injected into the small gap between two stacked wafers in vacuum ambient applying a mechanical pressure from both sides of wafers. Injected liquid adhesive was cured at 180ﾟC.This procesure improved the bondability of wafers and the electrical characteristics of micro-bumps.(c) Vertical interconnection and wafer thinningThe deep trench with the diameter of 3 mu m and the depth of 60 mum has been formed on a silicon substrate after optimizing the ICP(Inductively Coupled Plasma) etching condition. After the trench etching, oxidation, poly-silicon deposition, impurity diffusion and etching back of poly-silicon by CMP were performed. Thus, a low resistive vertical interconnection for three-dimensional integrated circuit has been successfully formed. Less