HIGH SPEED PARALLEL COMPUTER SYSTEM USING 3-DIMENTIONAL INTEGLATED SHARED MEMORY

该项目旨在为蒙特卡罗模拟开发一个紧凑的并行计算机系统。研究结果总结如下：1。专用于并行计算机系统的蒙特卡罗仿真。第一版并行计算机的系统分析已于1997年完成。第二种型号自1997年开始设计。在第二个版本中，为了加快处理器间的通信，对通信总线和协议进行了极大的改进。提出了一种新的环形母线管道结构，并将其引入到第二版设计中。通过环形总线来的数据在每个处理单元并行处理并发送到下一个处理单元。因此，环形母线和处理单元的组合系统就像一条巨大的管道。完成了体系结构的关卡设计。三维集成技术三维集成电路已开发出以下三个关键技术。(a)微隆起地层针对微隆起地层，开发了一种新的…More的举升技术。使用该技术可以很容易地形成小至5 μ m的铟（In）金（Au）微凸起。研究发现，在In-Au微凸点和铝电极之间插入薄钨膜可以有效地降低接触电阻。获得了极低的接触电阻，为0.05 ω /微凸点。(b)晶圆对准和粘合经过仔细的晶圆对准后，几个晶圆被堆叠和粘合以实现三维集成。提出了一种新的真空注胶方法用于硅片的粘接。在真空环境下，从晶圆片两侧施加机械压力，将液体胶粘剂注入两个堆叠晶圆片之间的小间隙中。注射液胶在180℃下固化。该工艺改善了晶圆的粘结性和微凸点的电学特性。(c)垂直互连和晶圆薄化优化ICP（电感耦合等离子体）蚀刻条件后，在硅衬底上形成了直径为3 μ m，深度为60 μ m的深沟槽。经过沟槽刻蚀后，对多晶硅进行氧化、沉积、杂质扩散和CMP刻蚀。因此，成功地形成了三维集成电路的低阻垂直互连。少

This project aimed to develop a compact parallel computer system specific for the Monte-Carlo simulation. The results are summarized as follows :1. Parallel computer system specific for the Monte-Carlo simulation. System ana1ysis of the first version parallel computer was completed on 1997. The second version has been designed since 1997. In second version, the communication bus and protocol are dramatically improved for speeding up the inter-processor communication. A new ring bus pipe line architecture is proposed and is introduced into the second version design. The data coming through the ring bus are processed at each processing unit in parallel and sent to next processing unit. Therefore, a combined system of ring bus and processing units act as a huge pipe line. The architecture level design has been completed.2. Three dimensional integration technologyThe following three key technologies have been developed for three-dimensional integrated circuit.(a) Micro-bump formationA new … More lift-off technology has been developed for the micro-bump formation. Indium(In)-gold(Au) micro-bumps as small as 5 mu m can be easily formed by using this technology. It was found that thin tungsten film inserted between In-Au micro-bump and aluminum electrode is very effective to reduce the contact resistance. A very low contact resistance of 0.05 OMEGA per micro-bump was obtained.(b) Wafer alignment and bondingSeveral wafers are stacked and bonded for three -dimensional integration after careful wafer alignment. A new vacuum adhesive injection method was developed for gluing the wafers. Liquid adhesive was injected into the small gap between two stacked wafers in vacuum ambient applying a mechanical pressure from both sides of wafers. Injected liquid adhesive was cured at 180ﾟC.This procesure improved the bondability of wafers and the electrical characteristics of micro-bumps.(c) Vertical interconnection and wafer thinningThe deep trench with the diameter of 3 mu m and the depth of 60 mum has been formed on a silicon substrate after optimizing the ICP(Inductively Coupled Plasma) etching condition. After the trench etching, oxidation, poly-silicon deposition, impurity diffusion and etching back of poly-silicon by CMP were performed. Thus, a low resistive vertical interconnection for three-dimensional integrated circuit has been successfully formed. Less