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Three-Dimensionarlly Stacked Optoelectronic System-on-Chip Fabricated Using Grapho-Assembly

使用图形组装制造的三维堆叠光电片上系统

基本信息

批准号：
21226009
负责人：
KOYANAGI Mitsumasa
金额：
$ 135.7万
依托单位：
Tohoku University
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (S)
财政年份：
2009
资助国家：
日本
起止时间：
2009-05-11 至 2014-03-31
项目状态：
已结题

项目摘要

Key technologies to achieve a 3D-stacked optoelectronic system-on-a chip (SOC) have been studied focusing on new grapho-assembly technology to achieve 3D stacking with high alignment accuracy and new 3D silicon photonics. We formed micro/nano-scale concavo-convex patterns on both upper and lower silicon chip surfaces and then these chips were precisely aligned making use of surface tension of liquid in the gapho-assembly. A high alignment accuracy of less than 0.1um has been achieved using the gapho-assembly. We have developed new technologies of TSPV (Through Si Photonic Via) and UDOC (Uni-Directional Optical Coupler). We successfully fabricated TSPV with a diameter of 10um showing excellent optical confinement. We proposed and fabricated a new optical grating coupler with side mirror. We confirmed that vertical optical signal propagated through TSPV was coupled to horizontal Si nano optical waveguide using this optical grating coupler with high coupling efficiency of more than 80%.

研究了实现3D堆叠的光电子片上系统（SOC）的关键技术，重点是实现具有高对准精度的3D堆叠的新图形组装技术和新的3D硅光子学。我们在上下硅片表面形成微/纳米级凹凸图案，然后利用间隙组装中液体的表面张力将这些芯片精确对准。使用该间隙组件实现了小于0.1 μ m的高对准精度。我们开发了TSPV（硅通孔）和UDOC（单向光耦合器）的新技术。我们成功地制备了直径为10 μ m的TSPV，表现出良好的光限域性能。提出并研制了一种新型的带侧镜的光栅耦合器。我们证实，垂直的光信号通过TSPV传输耦合到水平的硅纳米光波导使用这种光栅耦合器与高耦合效率超过80%。

项目成果

期刊论文数量（0）

专著数量（0）

科研奖励数量（0）

会议论文数量（0）

专利数量（0）

Fabrication tolerance evaluation of high efficient unidirectional optical coupler for though silicon photonic via in optoelectronic 3D-LSI

DOI：
10.1109/3dic.2012.6262957
发表时间：
2012-08
期刊：
2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International
影响因子：
0
作者：
A. Noriki;Kang-wook Lee;J. Bea;T. Fukushima;Tetsu Tanaka;M. Koyanagi
通讯作者：
A. Noriki;Kang-wook Lee;J. Bea;T. Fukushima;Tetsu Tanaka;M. Koyanagi

Minimization of the Local Residual Stress in 3D Flip Chip Structures by Optimizing the Mechanical Properties of Electroplated Materials and the Alignment Structure of TSVs and Fine Bumps