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THREE-DIMENSIONALLY STACKED IMAGE PROCESSING SYSTEM WITH LEARNING FUNCTION

具有学习功能的三维堆叠图像处理系统

基本信息

批准号：
09305023
负责人：
KOYANAGI Mitsumasa
金额：
$ 23.74万
依托单位：
TOHOKU UNIVERSITY
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (A)
财政年份：
1997
资助国家：
日本
起止时间：
1997 至 1999
项目状态：
已结题

来源：
https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-09305023/
关键词：
IMAGE PROCESSING REAL-TIME LEARNING ASSOCIATION NEURAL NETWORK PARALLEL PROCESSING 3D INTEGRATION WAFER BONDING 三次元積層技術

项目摘要

We have proposed a new image processing chip with three-dimensional structure. This chip consists of four layers of image sensor array, amplifier and AD converter array, resister (data latch) array and processor array. These four layers are connected vertically using high density of vertical interconnections. Therefore, 2D image signal data are simultaneously transferred in vertical direction and processed in parallel in each layer. In order to transfer the 2D output data from this chip to other chips with high speed and high efficiency, the 2D output data are compressed and reconstructed using a neural network. It was confirmed that the learning and association function of neural network is useful for the data compression and reconstruction. We have developed a new 3D integration technology to realize such image processing chip with learning and association function. In this 3D integration technology, the device wafer with the buried interconnections are glued to a quartz glass and then thinned from the back side using the mechanical grinding and CMP. The micro bumps are formed on the bottom of the buried interconnections at the back side. This thinned device wafer is glued to the another device wafer after a careful wafer alignment. By repeating this sequence, the 3D stacked wafer is obtained. We fabricated the 3D stacked image sensor test chip using this 3D integration technology. The electrical characteristics of this stacked 3D image sensor test chip were evaluated through the buried interconnections and micro bumps.

我们提出了一种新的图像处理芯片与三维结构。该芯片由图像传感器阵列、放大器和AD转换器阵列、电阻（数据锁存器）阵列和处理器阵列四层组成。这四个层使用高密度的垂直互连来垂直连接。因此，2D图像信号数据在垂直方向上被同时传送，并且在每层中被并行处理。为了将该芯片的二维输出数据高速、高效地传输到其他芯片，采用神经网络对二维输出数据进行压缩和重构。结果表明，神经网络的学习和联想功能有利于数据的压缩和重构。我们开发了一种新的3D集成技术来实现这种具有学习和联想功能的图像处理芯片。在这种3D集成技术中，具有掩埋互连的器件晶片被粘合到石英玻璃上，然后使用机械研磨和CMP从背面减薄。微凸块形成在背面的掩埋互连的底部上。在仔细的晶片对准之后，将该减薄的器件晶片胶合到另一器件晶片。通过重复该序列，获得3D堆叠晶片。利用这种三维集成技术制作了三维叠层图像传感器测试芯片。通过埋置互连和微凸点来评估该堆叠式3D图像传感器测试芯片的电特性。