THREE-DIMENSIONALLY STACKED IMAGE PROCESSING SYSTEM WITH LEARNING FUNCTION

提出了一种具有三维结构的新型图像处理芯片。该芯片由四层结构组成，分别是图像传感器阵列、放大器和AD转换器阵列、数据锁存器阵列和处理器阵列。这四层使用高密度的垂直互连进行垂直连接。因此，2D图像信号数据同时在垂直方向上传输，并在每一层中并行处理。为了将该芯片的2D输出数据高速高效地传输到其他芯片上，利用神经网络对2D输出数据进行了压缩和重构。证实了神经网络的学习和联想功能对数据的压缩和重构是有用的。为了实现这种具有学习和联想功能的图像处理芯片，我们开发了一种新的3D集成技术。在这种3D集成技术中，具有埋入互连的器件晶片被粘合在石英玻璃上，然后使用机械研磨和化学机械抛光从背面减薄。微凸点形成在背面埋入的互连的底部。这个变薄的器件晶片在仔细对准晶片后粘合到另一个器件晶片上。通过重复该序列，获得3D堆叠晶片。利用这种3D集成技术制作了3D堆叠式图像传感器测试芯片。通过埋入互连和微凸点对堆叠式3D图像传感器测试芯片的电学特性进行了评估。

We have proposed a new image processing chip with three-dimensional structure. This chip consists of four layers of image sensor array, amplifier and AD converter array, resister (data latch) array and processor array. These four layers are connected vertically using high density of vertical interconnections. Therefore, 2D image signal data are simultaneously transferred in vertical direction and processed in parallel in each layer. In order to transfer the 2D output data from this chip to other chips with high speed and high efficiency, the 2D output data are compressed and reconstructed using a neural network. It was confirmed that the learning and association function of neural network is useful for the data compression and reconstruction. We have developed a new 3D integration technology to realize such image processing chip with learning and association function. In this 3D integration technology, the device wafer with the buried interconnections are glued to a quartz glass and then thinned from the back side using the mechanical grinding and CMP. The micro bumps are formed on the bottom of the buried interconnections at the back side. This thinned device wafer is glued to the another device wafer after a careful wafer alignment. By repeating this sequence, the 3D stacked wafer is obtained. We fabricated the 3D stacked image sensor test chip using this 3D integration technology. The electrical characteristics of this stacked 3D image sensor test chip were evaluated through the buried interconnections and micro bumps.