Wafer Level Parallel Processing System Using Cubic Integration Technology

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In this work, we have developed basic technologies for the wafer level parallel processing system using the cubid integration technology.First of all, we developed the cubic integration technology to fabricate the three dimensional (3D) processor and the three dimensional (3D) shared memory. The 3D processor consists of the processor layer and the memory layers which are closely connected by vertical interconnections to solve the bus bottle neck between them. The 3D shared memory is a memory, in which several memory layers are stacked into one chip and closely connected each other by vertical interconnections. It can realize the parallel processing system without the bus bottle neck. We fabricated 3D processor and 3D shared memory and obtained excellent evaluation results. We also developed the optical interconnection technology to connect between chips in wafer level system. We could successfully demonstrate the optical data transfer operation between two chips on which a VCSEL and photodiodes are mounted.We successfully demonstrate the possibility of wafer level parallel processing system using the cubic integration technology in this work.