Wafer Level Parallel Processing System Using Cubic Integration Technology

采用三次积分技术的晶圆级并行处理系统

• 批准号: 11355015
• 负责人: KOYANAGI Mitsumasa
• 金额: $ 20.95万
• 依托单位: TOHOKU UNIVERSITY
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for Scientific Research (A)
• 财政年份: 1999
• 资助国家: 日本
• 起止时间: 1999 至 2001
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-11355015/
• 关键词: Three Dimensional Integration; Parallel Processing; Wafer Level Integration; System on a Chip; Optical Interconnection; Memory; Semiconductor; LSI; ウェーハ張り合わせ技術; ウエーハレベルインテグレーション; システムオンチップ; ウエーハ張り合わせ技術; マイクロバンプ

In this work, we have developed basic technologies for the wafer level parallel processing system using the cubid integration technology.First of all, we developed the cubic integration technology to fabricate the three dimensional (3D) processor and the three dimensional (3D) shared memory. The 3D processor consists of the processor layer and the memory layers which are closely connected by vertical interconnections to solve the bus bottle neck between them. The 3D shared memory is a memory, in which several memory layers are stacked into one chip and closely connected each other by vertical interconnections. It can realize the parallel processing system without the bus bottle neck. We fabricated 3D processor and 3D shared memory and obtained excellent evaluation results. We also developed the optical interconnection technology to connect between chips in wafer level system. We could successfully demonstrate the optical data transfer operation between two chips on which a VCSEL and photodiodes are mounted.We successfully demonstrate the possibility of wafer level parallel processing system using the cubic integration technology in this work.

在这项工作中，我们利用立方体集成技术开发了晶圆级并行处理系统的基本技术。首先，我们开发了三次积分技术来制造三维处理器和三维共享存储器。三维处理器由处理器层和存储层组成，通过垂直互连紧密连接，解决了处理器层和存储层之间的总线瓶颈问题。3D共享存储器是将多个存储器层堆叠在一个芯片上，并通过垂直互连紧密连接在一起的存储器。它可以实现无总线瓶颈的并行处理系统。制作了三维处理器和三维共享存储器，取得了优异的评价结果。我们还开发了用于晶圆级系统中芯片之间互连的光互连技术。我们成功地演示了安装VCSEL和光电二极管的两个芯片之间的光学数据传输操作。本文成功地论证了利用三次积分技术实现晶圆级并行处理系统的可能性。

项目成果

栗野浩之, 中川源洋, 李康旭, 中村共則, et al.: "三次元集積化技術を使ったビジョンチップ"社団法人 電子情報通信学会 信学技報. 101(85). 29-35 (2001)

Hiroyuki Kurino、Minahiro Nakakawa、Kang-woo Lee、Kiminori Nakamura 等人：“使用三维集成技术的视觉芯片”IEICE 技术报告，IEICE 101(85) (2001)。

栗原浩之, 中川源洋, 李康旭, 中村共則, et al.: "三次元集積化技術を使ったビジョンチップ"社団法人 電子情報通信学会 信学技報. 101(85). 29-35 (2001)

Hiroyuki Kurihara、Minahiro Nakakawa、Kang-woo Lee、Kimonori Nakamura 等人：“使用三维集成技术的视觉芯片”IEICE 技术报告，IEICE，101(85) (2001)。

K.W.Lee,T.Nakamura,K.T.Park,K.Y.Kim,H.Kurino,M.Koyanagi他3人: "Development of Three-Dimensional Integration Technology for Highly Parallel Image-Processing Chip"Jpn.J.Appl.Phys.Vol.39 No.4B. 印刷中 (2000)

K.W.Lee、T.Nakamura、K.T.Park、K.Y.Kim、H.Kurino、M.Koyanagi 等 3 人：“高度并行图像处理芯片的三维集成技术的开发”Jpn.J.Appl.Phys.Vol。 39 No.4B 印刷中（2000）

K-T. Park, T. Nakamura, K-W. Lee, H. Kurino, M. Koyanagi, et al.: "A WAFER-LEVEL THREE DIMENSIONAL CHIP STACKING TECHNOLOGY FOR HIGH-PERFORMANCE MICROELECTRONICS AND MEMS"Proc. of IPACK'01 The Pacific Rim/ASME Int. Electronic Packaging Technical Conferenc

K-T。

K.W.Lee,T.Nakamura,K.Sakuma H.Kurino M.Koyanagi,and et al.: "Development of Three-Dimensional Integration Technology for Highly Parallel Image-Processing Chip"Japanese Journal of Applied Physics. 39. 2473-2477 (2000)

K.W.Lee、T.Nakamura、K.Sakuma H.Kurino M.Koyanagi 等：“高度并行图像处理芯片的三维集成技术的开发”日本应用物理学杂志。