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High Performance Parallel Processor System Using Three-Dimensional Processor Chip

采用三维处理器芯片的高性能并行处理器系统

基本信息

批准号：
15106006
负责人：
KOYANAGI Mitsumasa
金额：
$ 73.3万
依托单位：
Tohoku University
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (S)
财政年份：
2003
资助国家：
日本
起止时间：
2003 至 2007
项目状态：
已结题

来源：
https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-15106006/
关键词：
Three-Dimensionally Stacked Processor Multiport Shared Memory Three-Dimensional Integration Wafer Bonding Optical Interconnection Optical Wave Guide Parallel Processing System High Speed Data Transfer ウェーハ張り合わせ

项目摘要

A new parallel processing system with shared memories was proposed. We designed a prototype system and evaluated its performance. Data to be shared are transferred to processor elements (PE's) through a high-speed multiport ring bus in this system. An optical interconnection is used as the high-speed multiport ring bus. The system performance was improved by using node-shared cache memories with three-dimensional structure which decreases the cache miss-hit rate. The performance increased almost in proportion to the number of PE.We developed two key technologies of optical interconnection and three-dimensional integration to realize the proposed system. We succeeded in fabricating the optical waveguide with an extremely low signal propagation loss of 0.029dB/cm. We achieved a high-speed data transfer rate of 10Gbps using this optical waveguide with the length of 5cm. We also developed a new beam-lead bonding technology to directly integrate photodetectors and VCSEL's on LSI chip. We fabricated a test module using these technologies in which SRAM cache memories were connected by this optical waveguide and confirmed the optical data transfer among these SRAM cache memories.Furthermore, we developed a three-dimensional integration technology based on wafer bonding. We succeeded in fabricating a three-dimensionally stacked microprocessor test chip for the first time in the world. We also fabricated a three-dimensionally stacked memory test chip with ten memory layers. In addition, we developed a new three-dimensional integration technology called a super-chip integration technology aiming to realize a further advanced system with stacked microprocessor and memory chips. We could stack various kinds of chips with different chip size and thickness by the super-chip integration.

提出了一种新的共享内存的并行处理系统。我们设计了一个原型系统，并对其性能进行了评估。在该系统中，要共享的数据通过高速多端口环形总线传输到处理器单元(PE)。采用光互连作为高速多端口环路总线。采用节点共享的三维结构缓存，降低了缓存未命中率，提高了系统性能。我们开发了光互连和三维集成两项关键技术来实现所提出的系统。我们成功地制作出了信号传输损耗极低的光波导，其信号传输损耗为0.029dB/cm。利用该长度为5 cm的光波导实现了10Gbps的高速数据传输。我们还开发了一种新的束流-引线键合技术，将光电探测器和VCSEL直接集成到LSI芯片上。利用这些技术制作了SRAM高速缓冲存储器通过光波导连接的测试模块，证实了这些SRAM高速缓冲存储器之间的光数据传输，并开发了基于晶片键合的三维集成技术。我们在世界上首次成功地制造了一个三维堆叠的微处理器测试芯片。我们还制作了一个具有10个存储层的三维堆叠式存储测试芯片。此外，我们开发了一种新的三维集成技术，称为超级芯片集成技术，旨在实现堆叠微处理器和存储芯片的进一步先进系统。通过超级芯片集成，我们可以堆叠各种不同芯片尺寸和厚度的芯片。

项目成果

期刊论文数量（138）

专著数量（0）

科研奖励数量（0）

会议论文数量（0）

专利数量（0）

ロボットビジョンシステムのための積層型並列リコンフィギャラブル画像処理プロセツサの設計

机器人视觉系统堆叠式并行可重构图像处理处理器设计

DOI：
发表时间：
2006
期刊：
電子情報通信学会論文誌 Vol. J89-D
影响因子：
0
作者：
山村正樹;狩野直和;川島隆幸;杉村武昭
通讯作者：
杉村武昭

Fundamental Properties of Organic Low-κ Dielectrics Usable in the Cu Damascene Process

可用于铜镶嵌工艺的有机低介电常数电介质的基本特性

DOI：
发表时间：
2005
期刊：
Japanese Journal of Applied Physics Vol. 44, No. 11
影响因子：
0
作者：
西岡将輝;小林清;濱川聡;佐藤剛一;井上朋也;T.Yasaka;S.Nishizawa他;Yutaka NOMURA
通讯作者：
Yutaka NOMURA

Design of a Novel Real-Shared Memory Module for High Performance Parallel Processor System with Shared Memory

一种用于共享内存高性能并行处理器系统的新型实共享内存模块设计

DOI：
发表时间：
2004
期刊：
International Conference on Advanced Information Networking and Applications
影响因子：
0
作者：
Z.Liu;J.Shim;H.Kurino;Mitsumasa Koyanagi
通讯作者：
Mitsumasa Koyanagi

Chip-to-Wafer Stacking for 3D Integration with TSV

用于与 TSV 进行 3D 集成的芯片到晶圆堆叠