High Performance Parallel Processor System Using Three-Dimensional Processor Chip

采用三维处理器芯片的高性能并行处理器系统

• 批准号: 15106006
• 负责人: KOYANAGI Mitsumasa
• 金额: $ 73.3万
• 依托单位: Tohoku University
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for Scientific Research (S)
• 财政年份: 2003
• 资助国家: 日本
• 起止时间: 2003 至 2007
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-15106006/
• 关键词: Three-Dimensionally Stacked Processor; Multiport Shared Memory; Three-Dimensional Integration; Wafer Bonding; Optical Interconnection; Optical Wave Guide; Parallel Processing System; High Speed Data Transfer; ウェーハ張り合わせ

A new parallel processing system with shared memories was proposed. We designed a prototype system and evaluated its performance. Data to be shared are transferred to processor elements (PE's) through a high-speed multiport ring bus in this system. An optical interconnection is used as the high-speed multiport ring bus. The system performance was improved by using node-shared cache memories with three-dimensional structure which decreases the cache miss-hit rate. The performance increased almost in proportion to the number of PE.We developed two key technologies of optical interconnection and three-dimensional integration to realize the proposed system. We succeeded in fabricating the optical waveguide with an extremely low signal propagation loss of 0.029dB/cm. We achieved a high-speed data transfer rate of 10Gbps using this optical waveguide with the length of 5cm. We also developed a new beam-lead bonding technology to directly integrate photodetectors and VCSEL's on LSI chip. We fabricated a test module using these technologies in which SRAM cache memories were connected by this optical waveguide and confirmed the optical data transfer among these SRAM cache memories.Furthermore, we developed a three-dimensional integration technology based on wafer bonding. We succeeded in fabricating a three-dimensionally stacked microprocessor test chip for the first time in the world. We also fabricated a three-dimensionally stacked memory test chip with ten memory layers. In addition, we developed a new three-dimensional integration technology called a super-chip integration technology aiming to realize a further advanced system with stacked microprocessor and memory chips. We could stack various kinds of chips with different chip size and thickness by the super-chip integration.

提出了一种新的具有共享存储器的并行处理系统。我们设计了一个原型系统，并评估其性能。在该系统中，要共享的数据通过高速多端口环形总线传送到处理器元件（PE）。光互连被用作高速多端口环形总线。通过采用节点共享的三维缓存结构，降低了该高速缓存的误命中率，提高了系统的性能。我们开发了光互连和三维集成两项关键技术来实现所提出的系统。我们成功地制作了光波导，具有极低的信号传输损耗为0.029dB/cm。利用这种长度为5cm的光波导实现了10 Gbps的高速数据传输速率。我们还开发了一种新的梁引线键合技术，直接集成光电探测器和VCSEL的LSI芯片。利用这些技术制作了一个测试模块，通过该光波导连接SRAM高速缓存存储器，并验证了这些SRAM高速缓存存储器之间的光数据传输。此外，我们还开发了一种基于晶片键合的三维集成技术。我们在世界上首次成功地制造了三维堆叠的微处理器测试芯片。我们还制作了一个三维堆叠的存储器测试芯片与十个存储器层。此外，我们开发了一种新的三维集成技术，称为超级芯片集成技术，旨在实现更先进的系统与堆叠的微处理器和存储器芯片。通过超芯片集成，可以堆叠出不同尺寸和厚度的各种芯片。

项目成果

ロボットビジョンシステムのための積層型並列リコンフィギャラブル画像処理プロセツサの設計

机器人视觉系统堆叠式并行可重构图像处理处理器设计

• 发表时间: 2006
• 期刊: 電子情報通信学会論文誌 Vol. J89-D
• 作者: 山村正樹;狩野直和;川島隆幸;杉村武昭
• 通讯作者: 杉村武昭

Fundamental Properties of Organic Low-κ Dielectrics Usable in the Cu Damascene Process

可用于铜镶嵌工艺的有机低介电常数电介质的基本特性

• 发表时间: 2005
• 期刊: Japanese Journal of Applied Physics Vol. 44, No. 11
• 作者: 西岡 将輝;小林 清;濱川 聡;佐藤 剛一;井上 朋也;T.Yasaka;S.Nishizawa他;Yutaka NOMURA
• 通讯作者: Yutaka NOMURA

Design of a Novel Real-Shared Memory Module for High Performance Parallel Processor System with Shared Memory

一种用于共享内存高性能并行处理器系统的新型实共享内存模块设计

• 发表时间: 2004
• 期刊: International Conference on Advanced Information Networking and Applications
• 作者: Z.Liu;J.Shim;H.Kurino;Mitsumasa Koyanagi
• 通讯作者: Mitsumasa Koyanagi

Chip-to-Wafer Stacking for 3D Integration with TSV

用于与 TSV 进行 3D 集成的芯片到晶圆堆叠

• 发表时间: 2007
• 作者: 陳 群;関 孝行;佐藤 清貴;内田 雅樹;定方 正毅;Takafumi Fukushima
• 通讯作者: Takafumi Fukushima

Sub-Atmospheric Chemical Vapor Deposition Process for Chip-to-Wafer 3-Dimensional Intergration

用于芯片到晶圆 3 维集成的低于大气压化学气相沉积工艺

• 发表时间: 2006
• 作者: Hirokazu;Kikuchi
• 通讯作者: Kikuchi