High Performance Parallel Processor System Using Three-Dimensional Processor Chip

采用三维处理器芯片的高性能并行处理器系统

基本信息

批准号：
15106006
负责人：
KOYANAGI Mitsumasa
金额：
$ 73.3万
依托单位：
Tohoku University
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (S)
财政年份：
2003
资助国家：
日本
起止时间：
2003 至 2007
项目状态：
已结题

来源：
https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-15106006/
关键词：
Three-Dimensionally Stacked Processor Multiport Shared Memory Three-Dimensional Integration Wafer Bonding Optical Interconnection Optical Wave Guide Parallel Processing System High Speed Data Transfer ウェーハ張り合わせ

项目摘要

A new parallel processing system with shared memories was proposed. We designed a prototype system and evaluated its performance. Data to be shared are transferred to processor elements (PE's) through a high-speed multiport ring bus in this system. An optical interconnection is used as the high-speed multiport ring bus. The system performance was improved by using node-shared cache memories with three-dimensional structure which decreases the cache miss-hit rate. The performance increased almost in proportion to the number of PE.We developed two key technologies of optical interconnection and three-dimensional integration to realize the proposed system. We succeeded in fabricating the optical waveguide with an extremely low signal propagation loss of 0.029dB/cm. We achieved a high-speed data transfer rate of 10Gbps using this optical waveguide with the length of 5cm. We also developed a new beam-lead bonding technology to directly integrate photodetectors and VCSEL's on LSI chip. We fabricated a test module using these technologies in which SRAM cache memories were connected by this optical waveguide and confirmed the optical data transfer among these SRAM cache memories.Furthermore, we developed a three-dimensional integration technology based on wafer bonding. We succeeded in fabricating a three-dimensionally stacked microprocessor test chip for the first time in the world. We also fabricated a three-dimensionally stacked memory test chip with ten memory layers. In addition, we developed a new three-dimensional integration technology called a super-chip integration technology aiming to realize a further advanced system with stacked microprocessor and memory chips. We could stack various kinds of chips with different chip size and thickness by the super-chip integration.

提出了一个具有共同记忆的新的并行处理系统。我们设计了一个原型系统并评估了其性能。要共享的数据通过该系统中的高速多层环总线传输到处理器元素（PE）。光学互连用作高速多层环总线。使用节点共享的缓存记忆具有三维结构，从而提高了系统性能，从而降低了缓存失误率。该性能几乎与PE数量相比提高。我们开发了两种关键的光学互连和三维整合技术，以实现所提出的系统。我们成功地制造了光波导，信号传播损失为0.029db/cm。我们使用此光学波导的长度为5厘米，达到了10Gbps的高速数据传输速率。我们还开发了一种新的光束铅键合技术，以直接将光电视图和VCSEL在LSI芯片上集成。我们使用这些技术制造了一个测试模块，在该技术中，该光学波导连接了SRAM缓存记忆，并确认了这些SRAM缓存记忆之间的光学数据传输。furthermore，我们根据晶圆键开发了三维整合技术。我们成功制造了世界上第一次制造三维堆积的微处理器测试芯片。我们还制造了一个具有十个内存层的三维堆叠内存测试芯片。此外，我们开发了一种新的三维集成技术，称为超芯片集成技术，旨在通过堆叠的微处理器和存储芯片实现进一步的先进系统。我们可以通过超芯片集成堆叠具有不同芯片尺寸和厚度的各种芯片。

项目成果

期刊论文数量（138）

专著数量（0）

科研奖励数量（0）

会议论文数量（0）

专利数量（0）

New three-dimensional integration technology using chip-to-wafer bonding to achieve ultimate super-chip integration

DOI：
10.1143/jjap.45.3030
发表时间：
2006-04-01
期刊：
JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS
影响因子：
0
作者：
Fukushima, Takafumi;Yamada, Yusuke;Koyanagi, Mitsumasa
通讯作者：
Koyanagi, Mitsumasa

Chip-to-Wafer Stacking for 3D Integration with TSV

用于与 TSV 进行 3D 集成的芯片到晶圆堆叠