Modeling of Impurity Diffusion in SOI Substrates for Future LSIs

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To develop the ultra thin SOI substrates which is expected as ones for future LSIs with higher speed and lower power performance, we studied (i) the accurate measurement method of carrier concentration profiles in SOIs, and (ii) estimation of crystalline quality of SOIs, and extraction of modeling parameters of impurity diffusion in SOIs for process simulation. Results obtained are as follows :(1) Carrier concentration profiles in SOIs were measured by spreading resistance method. For as-received p-and n-type SOI samples, there is a carrier-depleted (highly resistive ) layer near the interface of SOI and buried oxide. For samples annealed at high temperatures near 1000℃, the carrier-depleted layer changes to inversion layer for p-type SOIs and to accumulation layer for n-type SOIs. The changes with annealing can be explained by assuming the positive charge in buried oxide and the decrease of interface state density.(2) Phosphorus and boron diffusion profiles in ultra thin SOIs involving SIMOX, UNIBOND and Eltran were compared with those in bulk substrates. The diffusion in such SOIs is retarded, compared with that in bulk substrates. Among ultra thin SOIs the diffusion in SIMOX is most retarded, compared with that in other SOIs. The diffusion retardation rate is considered to reflect the crystalline quality of buried oxide interface and SOI substrate. Furthermore, diffusion modeling parameters for process simulation were extracted from the measured profiles in SOI.