Design of a Highly Integrated Neuro-Processor for Robot Control Based on the Hierarchical Redundancy Design Method

(1)非冗余神经处理器的设计面向智能机器人实时控制的全硬件神经处理器。完成了神经处理器的体系结构设计、逻辑设计和版图设计。估计了运算速度、芯片尺寸和单个晶片上集成的神经元数目。(2)分层冗余设计提出了适合神经处理器的分层冗余设计方法。该方法将神经元内部的电路级冗余与以神经元为基本构件的系统级冗余相结合。(3)冗余神经处理器的优化设计采用分层冗余设计的方法对神经处理器进行了成品率分析，明确了系统参数与成品率之间的关系。在此基础上，对神经处理器进行了优化设计。结果表明，一个由500个神经元组成的三层前馈神经处理器可以在一片晶片上实现，开销为27%，成品率为50%。

(1) Design of the Non-Redundant Neuro-ProcessorThe full-hardware neuro-processor applicable to real time control of intelligent robots is targeted. The architecture design, the logic design, and the layout design of the neuro-processor have been carried out. The operation speed, the chip size, and the number of neurons integrated on a single wafer are estimated.(2) Presentation of the Hierarchical Redundancy DesignThe hierarchical redundancy design methodology suitable for the neuro-processor is presented. This method combines the circuit level redundancy inside a neuron with the system level redundancy using a neuron as the basic building block. Using the method, the yield enhancement of the neuro-processor can be realized with small overhead.(3) Optimal Design of the Redundant Neuro-ProcessorThe yield analysis of the neuro-processor applying the hierarchical redundancy design has been carried out and the relationship between system parameters and the yield is made clear. Based on the analysis, the optimal design of the neuro-processor has been done. It is concluded that a 3-layered feed-forward neuro-processor composed of 500 neurons may be implemented on a single wafer with the overhead of 27% and with the yield of 50%.