Design of a Highly Integrated Neuro-Processor for Robot Control Based on the Hierarchical Redundancy Design Method

基于分层冗余设计方法的高度集成机器人控制神经处理器设计

• 批准号: 10650437
• 负责人: TOMABECHI Nobuhiro
• 金额: $ 1.28万
• 依托单位: Hachinohe Institute of Technology
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for Scientific Research (C)
• 财政年份: 1998
• 资助国家: 日本
• 起止时间: 1998 至 1999
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-10650437/
• 关键词: hierarchical redundancy design; WSI; neuro-procossor; yield enhancement; robot; control; 超高集積; 歩留り改善; 多次元サブシステム分割法

(1) Design of the Non-Redundant Neuro-ProcessorThe full-hardware neuro-processor applicable to real time control of intelligent robots is targeted. The architecture design, the logic design, and the layout design of the neuro-processor have been carried out. The operation speed, the chip size, and the number of neurons integrated on a single wafer are estimated.(2) Presentation of the Hierarchical Redundancy DesignThe hierarchical redundancy design methodology suitable for the neuro-processor is presented. This method combines the circuit level redundancy inside a neuron with the system level redundancy using a neuron as the basic building block. Using the method, the yield enhancement of the neuro-processor can be realized with small overhead.(3) Optimal Design of the Redundant Neuro-ProcessorThe yield analysis of the neuro-processor applying the hierarchical redundancy design has been carried out and the relationship between system parameters and the yield is made clear. Based on the analysis, the optimal design of the neuro-processor has been done. It is concluded that a 3-layered feed-forward neuro-processor composed of 500 neurons may be implemented on a single wafer with the overhead of 27% and with the yield of 50%.

(1)非冗余神经处理器的设计针对适用于智能机器人实时控制的全硬件神经处理器。完成了神经处理器的架构设计、逻辑设计和布局设计。估计了操作速度、芯片尺寸和单个晶圆上集成的神经元数量。(2)分层冗余设计的提出提出了适合神经处理器的分层冗余设计方法。该方法使用神经元作为基本构建块，将神经元内部的电路级冗余与系统级冗余结合起来。利用该方法，可以以较小的开销实现神经处理器良率的提高。(3)冗余神经处理器的优化设计对采用分层冗余设计的神经处理器进行了良率分析，明确了系统参数与良率之间的关系。根据分析，完成了神经处理器的优化设计。结论是，可以在单个晶圆上实现由500个神经元组成的三层前馈神经处理器，其开销为27%，良率为50%。

项目成果

苫米地宣裕: "全ハードウエア形高速ニューロプロセッサの設計"八戸工業大学情報システム工学研究所紀要. 10. 1-4 (1998)

Nobuhiro Tomabechi：“全硬件高速神经处理器的设计”八户工业大学信息系统工学研究所通报。10. 1-4 (1998)。

苫米地宣裕: "WSI規模高速ニューロプロセッサの階層冗長構成法"電子情報通信学会論文誌. J81-D-I,7. 933-936 (1998)

Nobuhiro Tomabechi：“WSI 规模高速神经处理器的分层冗余配置方法”，电子、信息和通信工程师学会汇刊 J81-D-I，933-936（1998 年）。

Y.Fujioka and N.Tomabechi: "Design of a wafer scale parallel processor for intelligent robot control based on the dynamic reconfiguration of multi-operand arithmetic units."Transactions of IEICE Japan D-I. vol.J82-D-I, no.4. 543-551 (1999)

Y.Fujioka 和 N.Tomabechi：“基于多操作数算术单元动态重构的智能机器人控制晶圆级并行处理器的设计。”IEICE 日本 D-I 汇刊。

Nobuhiro Tomabechi: "Hierarchical redundancy design for WSI neuro-processors"Proc. IEEE Asia Pacific Symp. On Circuits & Systems. 787-790 (1998)

Nobuhiro Tomabechi：“WSI 神经处理器的分层冗余设计”Proc。

Nobuhiro Tomabechi: "Multi-dimensional subsystem-dividing for yield enhancement in defect-tolerant WSI systems"Proc. IEEE Int. Symp. On Defect and Fault Tolerance in VLSI Systems. 40-45 (1999)

Nobuhiro Tomabechi：“多维子系统划分，以提高容错 WSI 系统的产量”Proc。