Design of a Super-ffigh'-Speed RSA Encryption Processor Based on the Residue Table for Redundant Binary Numbers

基于冗余二进制数残差表的超高速RSA加密处理器设计

• 批准号: 12650453
• 负责人: TOMABECHI Nobuhiro
• 金额: $ 1.15万
• 依托单位: Hacbinohe Institute of Technology
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for Scientific Research (C)
• 财政年份: 2000
• 资助国家: 日本
• 起止时间: 2000 至 2001
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-12650453/
• 关键词: RSA cryptsystem; high-speed; Dprocessor; redundant binary number; residue table; design

(1) Detailed Design of the Encryption ProcessorThe RSA encryption processor with following features is designed.【encircled 1】All the arithmetic operations are performed in the form of the redundant binary arithmetic.【encircled 2】Residue calculation is performed by table-look-up where the table is built in the hardware of the processor.Following results are obtained.【encircled 1】The operation speed is about 3 Mbits/sec when the key length, N is 1024 bits.【encircled 2】The speed is almost 60 times that of the conventional processors. ^【encircled 3】The order of the operation speed is O(NlogN). The order of the conventional processors is O(N^2).【encircled 4】The chip size is (4.3 x 10^5λ)x(5,63 x 10^5λ), where λ denotes the standard size in the layout design.(2) Defect-Tolerance Design of the ProcessorThe following method is presented.【encircled 1】The targeted system is designed in the bit-slice form, and a bit-slice is taken as the unit block for redundancy.【encircled 2】Redundant blocks are uniformly distributed among the non-redundant blocks.【encircled 3】The function of me defective block is stopped and is sifted to the neighboring block.(3) Pipelined Design of the ProcessorAll the partial products in the multiplier circuit are totaled using the combination of the binary tree structure with the array structure of the redundant binary adders. By the introduction pf the pipelining, fee encryption speed is greatly enhanced when the plaintext data is continuously input and the timing design becomes easy.

(1)加密处理器的详细设计设计了具有以下特点的RSA加密处理器。所有的算术运算都是以冗余二进制算术的形式进行的。[包围2]余数的计算是通过查表的方式进行的，其中表是在处理器的硬件中构建的。得到了以下结果。当密钥长度为N为1024比特时，运算速度约为3兆比特/秒。^[包围3]运算速度的顺序是O(NlogN)。传统处理器的阶数为O(N^2)。芯片尺寸为(4.3x10^5λ)x(5.63x10^5λ)，其中λ表示版图设计中的标准尺寸。(2)处理器的容错设计提出了以下方法。[包围1]目标系统采用位片形式设计，处理器的流水线设计采用二叉树结构和冗余二进制加法器的阵列结构相结合的方法对乘法器电路中的所有部分积求和。通过流水线的引入，明文数据连续输入时费用加密速度大大提高，时序设计变得容易。

项目成果

N.Tomabechi, T.Ito: "Defect-tolerance design of the high-speed RSA encryption processor with built-in table for residue calculation of redundant binary numbers"Proc. IEEE Int. Conf. on Electronics, Circuits & Systems. 267-271 (2001)

N.Tomabechi、T.Ito：“具有用于冗余二进制数余数计算的内置表的高速 RSA 加密处理器的缺陷容错设计”Proc。

N. Tomabechi, T. Ito: "Design of a high-speed RSA encryption processor based on the residue table for redundant binary numbers"Systemsand Computers in Japan.. Vol. 33, no. 5. 1-10 (2002)

N. Tomabechi、T. Ito：“基于冗余二进制数残差表的高速 RSA 加密处理器的设计”日本系统与计算机。

N.Tomabechi, T.Ito: "Defect-tolerance design of the high-speed RSA encryption processor with built-in table for residue calculation of redundant binaiy numbers"Proc. IEEE Int. Conf. on Electronics, Circuits & Systems. 267-271 (2001)

N.Tomabechi、T.Ito：“具有用于冗余二进制数余数计算的内置表的高速 RSA 加密处理器的缺陷容错设计”Proc。

N.Tomabechi, T.Ito: "Design of a high-speed RSA encryption processor with built-in table for residue calculation of redundant binary numbers"Proc. IEEE Int. Symp. on Circuits & Systems. V697-V700 (2000)

N.Tomabechi、T.Ito：“带有内置表的高速 RSA 加密处理器的设计，用于冗余二进制数的余数计算”Proc。

N. Tomabechi, T. Ito: "Desien of a high-speed RSA encryption processor with built-in table for residue calculation of redundant binary numbers"Proc. IEEE Int. Symp. On Circuits & Syst.. V697-V700 (2000)

N. Tomabechi、T. Ito：“高速 RSA 加密处理器的设计，具有用于冗余二进制数余数计算的内置表”Proc。