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Design of a Super-ffigh'-Speed RSA Encryption Processor Based on the Residue Table for Redundant Binary Numbers

Design of a Super-ffigh'-Speed RSA Encryption Processor Based on the Residue Table for Redundant Binary Numbers
基于冗余二进制数残差表的超高速RSA加密处理器设计
批准号:
12650453
负责人:
TOMABECHI Nobuhiro
金额:
$1.15万
依托单位国家:
日本
项目类别:
Grant-in-Aid for Scientific Research (C)
财政年份:
2000
资助国家:
日本
项目状态:
已结题
起止时间:
2000 至 2001

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中文摘要
翻译
(1)加密处理器的详细设计设计了具有以下特点的RSA加密处理器。所有的算术运算都以冗余二进制算术的形式执行。[圈2]余数计算是通过查表来进行的,查表是在处理器的硬件中建立的。[圈1]当密钥长度N为1024位时,操作速度约为3 Mbits/sec。[包围2]速度几乎是传统处理器的60倍。^[圈3]运算速度的阶数为O(NlogN)。时间复杂度为O(N^2)。[圆圈4]芯片尺寸为(4.3 x 10^5λ)x(5.63 x 10^5λ),其中λ表示布局设计中的标准尺寸。(2)加工机的缺陷容限设计提出了以下方法。目标系统采用位片形式设计,以位片为单位块进行冗余。[圆圈2]冗余块均匀分布在非冗余块之间。[圆圈3]停止该缺陷块的功能并将其筛选到相邻块。(3)处理器的流水线设计采用二叉树结构和冗余二进制加法器阵列结构相结合的方法,对乘法器电路中的所有部分积进行求和。通过流水线的引入,在明文数据连续输入的情况下,大大提高了加密速度,并且时序设计变得容易。
英文摘要
(1) Detailed Design of the Encryption ProcessorThe RSA encryption processor with following features is designed.【encircled 1】All the arithmetic operations are performed in the form of the redundant binary arithmetic.【encircled 2】Residue calculation is performed by table-look-up where the table is built in the hardware of the processor.Following results are obtained.【encircled 1】The operation speed is about 3 Mbits/sec when the key length, N is 1024 bits.【encircled 2】The speed is almost 60 times that of the conventional processors. ^【encircled 3】The order of the operation speed is O(NlogN). The order of the conventional processors is O(N^2).【encircled 4】The chip size is (4.3 x 10^5λ)x(5,63 x 10^5λ), where λ denotes the standard size in the layout design.(2) Defect-Tolerance Design of the ProcessorThe following method is presented.【encircled 1】The targeted system is designed in the bit-slice form, and a bit-slice is taken as the unit block for redundancy.【encircled 2】Redundant blocks are uniformly distributed among the non-redundant blocks.【encircled 3】The function of me defective block is stopped and is sifted to the neighboring block.(3) Pipelined Design of the ProcessorAll the partial products in the multiplier circuit are totaled using the combination of the binary tree structure with the array structure of the redundant binary adders. By the introduction pf the pipelining, fee encryption speed is greatly enhanced when the plaintext data is continuously input and the timing design becomes easy.
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N. Tomabechi, T. Ito: "Design of a high-speed RSA encryption processor based on the residue table for redundant binary numbers"Systemsand Computers in Japan.. Vol. 33, no. 5. 1-10 (2002)
N. Tomabechi、T. Ito:“基于冗余二进制数残差表的高速 RSA 加密处理器的设计”日本系统与计算机。
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共 12 条
    Design of a Gigabit RSA encryption processor based on redundant binary arithmetic
    • 批准号:
      15500050
    • 项目类别:
      Grant-in-Aid for Scientific Research (C)
    • 资助金额:
      $1.22万
    • 财政年份:
      2003
    • 负责人:
      TOMABECHI Nobuhiro
    • 依托单位:
    Design of a Highly Integrated Neuro-Processor for Robot Control Based on the Hierarchical Redundancy Design Method
    • 批准号:
      10650437
    • 项目类别:
      Grant-in-Aid for Scientific Research (C)
    • 资助金额:
      $1.28万
    • 财政年份:
      1998
    • 负责人:
      TOMABECHI Nobuhiro
    • 依托单位:
    DESIGN OF A HIGHLY ROBOT CONTROL PROCESSOR BY INTRODUCING REDUNDANCY
    海外基金