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DESIGN OF A HIGHLY ROBOT CONTROL PROCESSOR BY INTRODUCING REDUNDANCY

DESIGN OF A HIGHLY ROBOT CONTROL PROCESSOR BY INTRODUCING REDUNDANCY
引入冗余的高度机器人控制处理器的设计
批准号:
08650505
负责人:
TOMABECHI Nobuhiro
金额:
$0.9万
依托单位国家:
日本
项目类别:
Grant-in-Aid for Scientific Research (C)
财政年份:
1996
资助国家:
日本
项目状态:
已结题
起止时间:
1996 至 1997

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中文摘要
翻译
(1)冗余互连线和交换开关的硬件对WSI成品率提高的影响冗余互连线和交换开关是WSI的重要组成部分,但在成品率分析中往往被忽略,本文分析了硬件对WSI成品率提高的影响。(2)提出了一种将系统分成两个方向的冗余设计方法,表明这种方法可以提高目标系统的成品率。高度集成的机器人控制处理机的设计在以前的研究中,处理机单元(PE)已被设计成集成在一个VLSI芯片上。在本研究中,高度集成的处理机由20- 30个处理机单元组成。在单片上设计了100个PE,PE之间的数据传输通过多条总线进行,以便在任何时候都能有效地操作所有集成的PE。提出了一种以动态划分为特征的多条总线的有效设计。高集成度机器人控制处理器的缺陷修复实现高集成度处理器的最大困难是成品率降低针对这一问题,提出了一种有效利用处理器可重构体系结构的缺陷恢复设计,研究发现,由PE构成的处理器,(84个PE有效)研究了高集成度处理器在机器人控制中的应用,发现在机器人控制中,大大减少。
英文摘要
Analysis of the yield enhancement of WSI by introducibg redundancy (1)The effect of the hardware of the redundant interconnection lines and the exchanging switches Although the redundant interconnection lines and the exchanging switches essential for redundant structure, they are usually neglected in the yield analysis.This study analyzes the effect of the hardware on the yield enhancement of WSI.(2)2-dimensional sudsystem-dividing A redundancy design in which a system is divided into two directions is proposed.It is made clear that the yield of the target system can be enhanced by this desing.Design of a highly integrated robot control processor In the preceding study.a processor element (PE)had been designed to be integrated on a VLSI chip In this study.a highly integrated processor composed 20-100 PEs is designed on a single wafer.The data transfer between PEs is designed to perform through the multiple buses so as to operate all of the fntegrated PE effectively at any time.An efficient design of the multiple buses characterized by the dynamic dividing is proposed.Defect recovery of the highly integrated robot control processor The most difficult problem in realizing the highly integrated processor is decreased yield resulting from increased production defects.Against this study proposes a defect recovery desing in which the reonfigurable architecture of the processor is effectively utilised.It is found that a processor composed of PEs (84 PEs are effective) may be implemented on a single wafer.The application of the highly integrated processor to the robot control is also studied and it is found that the delay time in operation can be greatly reduced.
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通讯作者:
苫米地宣裕: "冗長化VLSIの歩留りに対する冗長配線と切換スイッチのハードウエア量の影響" 電子情報通信学会論文誌D-I. J80-D-I,4(4月号掲載予定). (1997)
Nobuhiro Tomabechi:“冗余接线和转换开关硬件数量对冗余 VLSI 产量的影响”IEICE Transactions D-I,4(计划于 4 月出版)(1997 年)。
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苫米地宣裕: "擬似3次元サブシステム分割冗長VLSIの救済可否判定アルゴリズム" 八戸工業大学情報システム工学研究所紀要. 9巻. 1-8 (1997)
Nobuhiro Tomabechi:“确定伪 3D 子系统分区冗余 VLSI 的可挽救性的算法”八户工业大学信息系统工学研究所公告 9. 1-8 (1997)。
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苫米地 宣裕, 藤岡 与周: "知能ロボット制御用再構成可能並列ULSI/WSIプロセッサ" 電子情報通信学会技術研究報告. VLD97-107,4. 53-60 (1997)
Nobuhiro Tomabechi、Yoshu Fujioka:“用于智能机器人控制的可重构并行 ULSI/WSI 处理器” IEICE 技术研究报告 53-60 (1997)。
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共 17 条
    Design of a Gigabit RSA encryption processor based on redundant binary arithmetic
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      15500050
    • 项目类别:
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    • 资助金额:
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    • 财政年份:
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    • 负责人:
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    • 依托单位:
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    • 批准号:
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    • 项目类别:
      Grant-in-Aid for Scientific Research (C)
    • 资助金额:
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    • 财政年份:
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    • 负责人:
      TOMABECHI Nobuhiro
    • 依托单位:
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    • 批准号:
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    • 项目类别:
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    • 资助金额:
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    • 财政年份:
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