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Source and drain structures for InSb MISFETs

InSb MISFET 的源极和漏极结构

基本信息

批准号：
11650316
负责人：
SUGIURA Osamu
金额：
$ 1.86万
依托单位：
Tokyo Institute of Technology
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (C)
财政年份：
1999
资助国家：
日本
起止时间：
1999 至 2000
项目状态：
已结题

项目摘要

Suitable source and drain structures for short channel InSb MISFETs were investigated. As donor impurity predeposition, Sulfur adsorption and thin tin film evaporation were examined. A light-irradiating anneal was used for diffusion and activation of the donor dopants. Rectify ratio of 10^4 was obtained by tin doping in p-type InSb substrates. Employing the doping method, InSb MISFETs were fabricated in self-alignment way. Without annealing after fabrication, the transistor did not show the transistor characteristics. However, after annealing with light-irradiation, the transistor was operated in n-channel mode. The mobility was a few cm^2/Vs, that is very small, and there was the large leakage current through drain junctions. Improving the process by reducing the annealing temperature and by reducing gate insulator thickness, transistors showed high mobility. The highest mobility was 1500 cm^2/Vs. This is explained by that alloy spikes were formed during high temperature annealing (300 ℃) and that the spike shunt the junction. Low temperature annealing (200 ℃) seems to be suitable for forming uniform junctions. The threshold voltage of transistors with normal mask patterns were lower than that of transistors with ring gate patterns. It means that gate electrodes protect InSb interface from light-irradiating. Because, thermally damaged MIS diodes commonly show negative voltage shift in C-V characteristics. Normal pattern transistors has the pass between source and dram which is not covered by gate electrode. The InSb interface under the pass was damaged during light-irradiating anneal and showed negative threshold voltages. This is the evidence that gate electrodes act as mask in the annealing process.

研究了短沟道InSb MISFET的源漏结构。作为施主杂质的预沉积，研究了硫吸附和锡薄膜蒸发。光照射退火用于扩散和激活的施主掺杂剂。在p型InSb衬底上进行掺锡，获得了10^4的整流比。采用这种掺杂方法，以自对准方式制备了InSb MISFET。在制造后没有退火，晶体管没有显示出晶体管特性。然而，在用光照射退火之后，晶体管以n沟道模式操作。迁移率为几cm ^2/Vs，这是非常小的，并且存在通过漏极结的大的漏电流。通过降低退火温度和减少栅极绝缘体厚度来改进工艺，晶体管显示出高迁移率。最高迁移率为1500 cm ^2/Vs。这是由于合金尖峰在高温退火（300 ℃）过程中形成，并且尖峰对结进行了分流。低温退火（200 ℃）似乎适合于形成均匀的结。具有正常掩模图案的晶体管的阈值电压低于具有环形栅极图案的晶体管的阈值电压。这意味着栅电极保护InSb界面免受光照射。因为，热损伤的MIS二极管通常在C-V特性中显示负电压漂移。常规模式晶体管在源极和漏极之间具有不被栅极电极覆盖的通路。在光辐照退火过程中，道次下的InSb界面被破坏，并显示出负阈值电压。这是栅电极在退火过程中充当掩模的证据。