Development of Self Aligned Fabrication Process of High-Permittivity Gate Insulating Film for Low Consumption LSI

本课题的目的是建立一种自对准工艺，制备SiO_2等效氧化物厚度（EOT）小于1.0nm的高介电常数薄膜。该工艺采用等离子体氧化、Hf金属沉积、电子回旋共振（ECR）等离子体氧化Hf金属，然后通过精确控制氧的浓度进行沉积后退火。本研究的目标是实现漏电流比SiO_2低四个数量级、界面性质与SiO_2相似的高k薄膜。实验结果如下：采用Ar/O_2混合等离子体（最佳条件：O_2/Ar = 0.1/30 scccm）制备1.1.2 nm厚SiO_2，ECR溅射沉积3 nm厚Hf金属，然后在不破坏真空的条件下进行Hf金属氧化，最后进行快速热退火。当Hf氧化时间为8.5min，退火温度为650 ℃时，薄膜的EOT最低，为1.1nm 关于我们 r 30 s时，其漏电流密度比SiO_2低4个数量级。XPS分析表明，沉积的HfO_x转变为HfO_2，SiO_2与HfO_2反应，SiO_2厚度减小，形成Hf硅酸盐。2.为了将TaN薄膜用作MOSFET的栅金属，采用磁控溅射法沉积TaN薄膜，并通过后续退火工艺对TaN薄膜进行优化。结果表明，TaN薄膜使我们能够在低于750 ℃的温度下制备MOSFET。采用Hf金属掩模对TaN膜进行湿法化学刻蚀，成功制备出沟道长度为5 μ m的MOSFET。3.建立了以TaN为金属栅、Hf氧化物为高k绝缘膜的金属栅/高k/Si-MOSFET的制备工艺。与相同物理厚度的SiO_2薄膜相比，MOSFET的性能提高了40%。少

This subject aims to establish the self-aligned process for high permittivity films having the SiO_2 equivalent oxide thickness (EOT) of less than 1.0 nm, which is fabricated by the plasma oxidation, Hf metal deposition, and oxidation of Hf metal using electron cyclotron resonance (ECR) plasma and followed by the post deposition anneals by the precise control of oxygen. The target of this study is to embody the high-k film of which the leak current is four orders of magnitude lower than that of SiO_2 and also the interface property is similar to that of SiO_2. The obtained results are summarized as follows :1.1.2 nm thick SiO_2 fabrication by Ar/O_2 mixed plasma (optimum condition : O_2/Ar=0.1/30 scccm), 3 nm thick Hf metal deposition by ECR sputtering, and subsequent oxidation of Hf metal were carried out in the chamber without breaking vacuum, which was followed by rapid thermal anneal. The lowest EOT of 1.1 nm was obtained for the Hf oxidation of 8.5 min and the annealing of 650℃ fo … More r 30 s, in which the leak current density was four orders of magnitude lower than that of SiO_2. According to XPS measurements, it was found that the deposited HfO_x changes to HfO_2 and simultaneously the decrease of SiO_2 thickness and the formation of Hf silicate occur by the reaction of SiO_2 with Hf.2.In order to use the TaN film for the gate metal of MOSFET, the TaN film was deposited by magnetron sputtering and optimized by the subsequent annealing. It was found that the TaN film enable us to use the processing at temperatures less than 750℃ in MOSFET fabrication. The etching of the TaN film was successfully established by the wet chemical etching with the Hf metal mask, leading to the MOSFET fabrication having channel length of 5 μm.3.The fabrication process for metal-gate/high-k/Si-MOSFET was well established, which was employed TaN as metal gate and Hf oxide as high-k insulating film. The MOSFET showed the 40% increment of the performance, compared with that of SiO_2 having the same physical thickness as high-k film. Less