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Establishment of scaling technique of high-k gate dielectrics for low-power-consumption LSI

低功耗LSI用高k栅介质微缩技术的建立

基本信息

批准号：
18360152
负责人：
NAKASHIMA Hiroshi
金额：
$ 10.28万
依托单位：
Kyushu University
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (B)
财政年份：
2006
资助国家：
日本
起止时间：
2006 至 2007
项目状态：
已结题

来源：
https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-18360152/
关键词：
High permittivity insulating film silicon Electron cyclotron resonance Low-power-consumption LSI Hf oxide Metal gate TaN Effective work function 省電カLSI Hf酸化膜

项目摘要

This subject aims to establish gate stack integration with metal-gate/high-k film/S_1 structure for future MOSFET with very low SiO_2 equivalent oxide thickness (EOT). The goals were the leakage current decrease of 6 orders relative to S_1O_2 with the same EOT and the same interface quality as SiO_2/Si The obtained results are summarized as follows:1. SiO_2(15nm)/S_1 structure was first formed by thermal oxidation and subsequent etching Hf metal deposition and oxidation for SiO_2/S_1 structure were performed by using electron cyclotron resonance (ECR) plasma, which was followed by the post deposition annealing to induce the solid state reaction between HfO_x and SiO_2 As a results, EOT=115 nm and 4 orders decrease of leakage current could be achieved for fabricated TaN/HfO_2/HfSiO/S_1structure, Also, interface density (D_it) evaluation was performed by using DLTS, and D_it was 1× 10^<11>cm^<-2> eV^<-1>, which is similar to that of SiO_2/Si.2.In order to establish process integration of metal gate, the etching methods and the effective work functions φ_eff of various metals such as Au, Pt, HfN, TaN, Al, and Hf on S_1O_2 and HfO_2 were studied in detail As a result, it was clarified that φ_eff for Au and Pt have high values of 5 0 eV, φ_eff for HfN and TaN have middle values of 4 5 eV, and cm for Al and Hf have low values 0.40 eV Through these investigations, the threshold voltage control for n-and p-channel MOSFET became possible.3.The process integration for TaN/high-k/S_1-MOSFET was well established The fabricated MOSFET showed the normal operation Also, it was clarified that the degradation of interface quality and mobility caused by TaN deposition could be improved by relatively high temperature annealing.

本课题旨在为未来极低SiO_2等效氧化层厚度（EOT）的MOSFET建立金属栅/高k膜/S_1结构的栅堆叠集成。目标是在与SiO_2/Si相同的EOT和相同的界面质量下，漏电流相对于S_1O_2降低6个数量级。首先采用热氧化和刻蚀的方法形成SiO_2（15 nm）/S_1结构，然后采用电子回旋共振（ECR）等离子体进行Hf金属沉积和SiO_2/S_1结构的氧化，并在沉积后进行退火，诱导HfO_x和SiO_2之间的固相反应。用DLTS测试了TaN/HfO_2/HfSiO/S_1结构的界面密度（D_it），D_it为1× 10 ~（-1）cm ~（-1）eV ~（-1），与SiO_2/SiO_2/HfSiO/SiO_2结构的界面<11><-2>密度相近<-1>。为了实现金属栅的工艺集成，对S_1O_2和HfO_2上的Au、Pt、HfN、TaN、Al和Hf等金属的刻蚀方法和有效功函数φ_eff进行了详细的研究。结果表明，Au和Pt的φ_eff值都很高，为5 0 eV，HfN和TaN的φ eff值居中，为4.5eV，Al和Hf的φ eff值较低，为0.40eV。通过这些研究，使n沟道和p沟道MOSFET的阈值电压控制成为可能。阐明了由TaN沉积引起的界面质量和迁移率的劣化可以通过相对高温退火来改善。