Establishment of scaling technique of high-k gate dielectrics for low-power-consumption LSI

本课题旨在为未来极低SiO_2等效氧化厚度（EOT）的MOSFET建立具有金属栅极/高k膜/S_1结构的栅极堆叠集成。目标是在与SiO_2/Si具有相同EOT和相同界面质量的情况下，使泄漏电流相对于s_o_2降低6个数量级。采用热氧化法形成SiO_2(15nm)/S_1结构，然后蚀刻Hf金属沉积，利用电子回旋共振（ECR）等离子体氧化SiO_2/S_1结构，然后采用沉积后退火法诱导HfO_x与SiO_2之间的固相反应。结果表明，制备的TaN/HfO_2/HfSiO/S_1结构的EOT=115 nm，泄漏电流降低了4个量级。利用DLTS对界面密度（D_it）进行了评估，D_it为1× 10^<11>cm^<-2> eV^<-1>，与SiO_2/Si.2相似。为了建立流程集成的金属门,蚀刻的方法和有效的工作函数φ_eff各种金属,如非盟、Pt, HfN, TaN,和高频S_1O_2和HfO_2详细研究结果,阐明,φ_eff盟和Pt值高的5 0 eV,φ_eff HfN和棕褐色的中间值4 5 eV,和cm和高频低价值0.40 eV通过这些调查,阈值电压控制n和p沟道MOSFET成为possible.3。结果表明，TaN/high-k/S_1-MOSFET的工艺集成得到了很好的验证，制备的MOSFET能够正常工作，并且通过相对高温的退火可以改善由TaN沉积引起的界面质量和迁移率的下降。

This subject aims to establish gate stack integration with metal-gate/high-k film/S_1 structure for future MOSFET with very low SiO_2 equivalent oxide thickness (EOT). The goals were the leakage current decrease of 6 orders relative to S_1O_2 with the same EOT and the same interface quality as SiO_2/Si The obtained results are summarized as follows:1. SiO_2(15nm)/S_1 structure was first formed by thermal oxidation and subsequent etching Hf metal deposition and oxidation for SiO_2/S_1 structure were performed by using electron cyclotron resonance (ECR) plasma, which was followed by the post deposition annealing to induce the solid state reaction between HfO_x and SiO_2 As a results, EOT=115 nm and 4 orders decrease of leakage current could be achieved for fabricated TaN/HfO_2/HfSiO/S_1structure, Also, interface density (D_it) evaluation was performed by using DLTS, and D_it was 1× 10^<11>cm^<-2> eV^<-1>, which is similar to that of SiO_2/Si.2.In order to establish process integration of metal gate, the etching methods and the effective work functions φ_eff of various metals such as Au, Pt, HfN, TaN, Al, and Hf on S_1O_2 and HfO_2 were studied in detail As a result, it was clarified that φ_eff for Au and Pt have high values of 5 0 eV, φ_eff for HfN and TaN have middle values of 4 5 eV, and cm for Al and Hf have low values 0.40 eV Through these investigations, the threshold voltage control for n-and p-channel MOSFET became possible.3.The process integration for TaN/high-k/S_1-MOSFET was well established The fabricated MOSFET showed the normal operation Also, it was clarified that the degradation of interface quality and mobility caused by TaN deposition could be improved by relatively high temperature annealing.