Establishment of scaling technique of high-k gate dielectrics for low-power-consumption LSI

低功耗LSI用高k栅介质微缩技术的建立

基本信息

批准号：
18360152
负责人：
NAKASHIMA Hiroshi
金额：
$ 10.28万
依托单位：
Kyushu University
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (B)
财政年份：
2006
资助国家：
日本
起止时间：
2006 至 2007
项目状态：
已结题

来源：
https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-18360152/
关键词：
High permittivity insulating film silicon Electron cyclotron resonance Low-power-consumption LSI Hf oxide Metal gate TaN Effective work function 省電カLSI Hf酸化膜

项目摘要

This subject aims to establish gate stack integration with metal-gate/high-k film/S_1 structure for future MOSFET with very low SiO_2 equivalent oxide thickness (EOT). The goals were the leakage current decrease of 6 orders relative to S_1O_2 with the same EOT and the same interface quality as SiO_2/Si The obtained results are summarized as follows:1. SiO_2(15nm)/S_1 structure was first formed by thermal oxidation and subsequent etching Hf metal deposition and oxidation for SiO_2/S_1 structure were performed by using electron cyclotron resonance (ECR) plasma, which was followed by the post deposition annealing to induce the solid state reaction between HfO_x and SiO_2 As a results, EOT=115 nm and 4 orders decrease of leakage current could be achieved for fabricated TaN/HfO_2/HfSiO/S_1structure, Also, interface density (D_it) evaluation was performed by using DLTS, and D_it was 1× 10^<11>cm^<-2> eV^<-1>, which is similar to that of SiO_2/Si.2.In order to establish process integration of metal gate, the etching methods and the effective work functions φ_eff of various metals such as Au, Pt, HfN, TaN, Al, and Hf on S_1O_2 and HfO_2 were studied in detail As a result, it was clarified that φ_eff for Au and Pt have high values of 5 0 eV, φ_eff for HfN and TaN have middle values of 4 5 eV, and cm for Al and Hf have low values 0.40 eV Through these investigations, the threshold voltage control for n-and p-channel MOSFET became possible.3.The process integration for TaN/high-k/S_1-MOSFET was well established The fabricated MOSFET showed the normal operation Also, it was clarified that the degradation of interface quality and mobility caused by TaN deposition could be improved by relatively high temperature annealing.

该主题旨在与金属/高k膜/S_1结构建立栅极堆栈集成，用于未来的MOSFET，SIO_2等效的氧化物厚度（EOT）。目标是相对于S_1O_2的泄漏电流降低为6个订单，其EOT相同，并且与SIO_2/SI相同的接口质量总结了所获得的结果如下：1。首先通过热氧化和随后的蚀刻HF金属沉积和SIO_2/S_1结构蚀刻的SIO_2（15nm）/S_1结构，该结构是通过使用电子回旋谐振（ECR）等离子体来形成的。对于制造的tan/hfo_2/hfsio/s_1结构，可以实现泄漏电流的界面密度（d_it）评估1×10^<11> cm^<-2> ev^<-1>，这与Sio_2/si.2的相似之处相似，以建立多个金属登机的过程，并有效地建立一个eTcem and eTCH a efferations and eTcription and eTcription and eTce a eff a eff a efferage and eff a eff a eff a effertim and。 Pt, HfN, TaN, Al, and Hf on S_1O_2 and HfO_2 were studied in detail As a result, it was clarified that φ_eff for Au and Pt have high values of 5 0 eV, φ_eff for HfN and TaN have middle values of 4 5 eV, and cm for Al and Hf have low values 0.40 eV Through these investigations, the threshold voltage control for n-and p-channel MOSFET 3. tan/High-k/s_1-mosfet的过程集成得出了很好的确定，制造的MOSFET也显示出正常的操作，可以通过相对较高的温度退火来改善界面质量和tan沉积造成的界面质量和迁移率的降解。