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A Study on Reconstructing Memory Hierarchy that Utilizes Emerging Devices

A Study on Reconstructing Memory Hierarchy that Utilizes Emerging Devices
利用新兴设备重建内存层次结构的研究
批准号:
23650026
负责人:
SATO Toshinori
金额:
$2.25万
依托单位:
依托单位国家:
日本
项目类别:
Grant-in-Aid for Challenging Exploratory Research
财政年份:
2011
资助国家:
日本
项目状态:
已结题
起止时间:
2011 至 2013

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中文摘要
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英文摘要
Processor performance is still improved in order to achieve increasing performance demand. However, computer system can not provide us with enough performance to meet the demand. This is due to the poor performance of memory system. In addition, memory consumes huge power. Considering the above, we started our project.We assume that we can use next-generation memory devices such as STT-MRAM. Under this assumption, we try to reconstruct memory hierarchy in order to achieve high-performance, low-power, and dependable memory system.The proposed memory system can improve energy-delay product by up to 49%.
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DOI: --
发表时间: 2012
期刊:
影响因子: --
作者: [小川哲平, 林田隆則, 佐藤寿倫]
通讯作者: 佐藤寿倫
佐藤研究室
佐藤实验室
DOI: --
发表时间:
期刊:
影响因子: --
作者: []
通讯作者:
DOI: --
发表时间: 2013
期刊:
影响因子: --
作者: [吉田康洋, 林田隆則, 佐藤寿倫]
通讯作者: 佐藤寿倫
スーパスカラ型CPUコアの低消費電力化手法の提案
降低超标量CPU内核功耗方法的提出
DOI: --
发表时间: 2012
期刊:
影响因子: --
作者: [柴田善水, 林田隆則, 佐藤寿倫, 高橋伸弥]
通讯作者: 高橋伸弥
11
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