Research on improving energy efficiency of embedded processors in ubiquitous information devices

提高普适信息设备嵌入式处理器能效的研究

基本信息

项目摘要

Power consumption is a major concern in embedded microprocessors design. Reducing power has also been a critical design goal for general-purpose microprocessors. Since they require high performance as well as low power, power reduction at the cost of performance cannot be accepted. There are a lot of device-level techniques that reduce power with maintaining performance. They select non-critical paths as candidates for low-power design, and performance-oriented design is used only in speed-critical paths. The same philosophy can be applied to architectural-level design. We evaluate a technique, which exploits dynamic information regarding instruction criticality in order to reduce power. We evaluate an instruction steering policy for a clustered microarchitecture, which is based on instruction criticality, and find it is substantially energy-efficient while it suffers performance degradation.In the deep submicron (DSM) semiconductor technologies, a conservative approach called "worst-case design" will not work very soon. The DSM increases noise and process variations and requires supply voltage reduction, and thus reduces design margins that worst-case design methodologies require. We have to design microprocessors by considering typical case rather than worst case. The Constructive Timing Violation (CTV) paradigm is such a design methodology, where designers are focusing on typical cases rather than worrying about very rare worst cases. We have designed two types of ALUs that utilize the CTV, each of which has its own problems in size and in speed. In order to solve the problems, we propose to utilize an adder-comparator as the fault detection circuit. Using Verilog-HDL, we implement a carry select adder that utilizes the CTV, and evaluate it on logic simulations after logic synthesis with delay information. It is observed that substaintial improvement in energy efficiency is achieved.
功耗是嵌入式微处理器设计中的一个主要问题。降低功耗也是通用微处理器的一个重要设计目标。由于它们需要高性能和低功耗,因此不能接受以牺牲性能为代价的功耗降低。有很多设备级技术可以在保持性能的同时降低功耗。他们选择非关键路径作为低功耗设计的候选路径,而面向性能的设计仅用于速度关键路径。同样的理念也可以应用于建筑级别的设计。我们评估了一种技术,该技术利用关于指令关键程度的动态信息来降低功耗。在深亚微米(DSM)半导体技术中,基于指令关键度的集群微体系结构指令转向策略在性能下降的情况下具有较高的能效,但在深亚微米(DSM)半导体技术中,一种称为最坏情况设计的保守方法不会很快奏效。DSM增加了噪声和工艺变化,需要降低电源电压,从而降低了最坏情况下的设计方法所需的设计裕度。我们必须考虑典型情况而不是最坏情况来设计微处理器。构造性时序冲突(CTV)范例就是这样一种设计方法,在这种设计方法中,设计师专注于典型情况,而不是担心非常罕见的最坏情况。我们设计了两种利用CTV的ALU,每一种在大小和速度上都有自己的问题。为了解决这些问题,我们提出了使用加法器-比较器作为故障检测电路。使用Verilog-HDL语言实现了一个利用CTV的进位选择加法器,并对其进行了带延迟信息的逻辑综合后的逻辑仿真。观察到,能源效率得到了实质性的提高。

项目成果

期刊论文数量(0)
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An Energy-Efficient Instruction Scheduling Technique Exploiting Cache Miss Information
一种利用缓存未命中信息的节能指令调度技术
An Energy-Efficient Clustered Superscalar Processor
一种高能效集群超标量处理器
  • DOI:
  • 发表时间:
    2005
  • 期刊:
  • 影响因子:
    0
  • 作者:
    梶原慎太郎;小池英樹;福地健太郎;岡兼司;佐藤洋一;Toshinori Sato et al.
  • 通讯作者:
    Toshinori Sato et al.
データの重要度を利用するキャッシュメモリの省電力化
利用数据重要性实现高速缓存节能
Energy-Efficient Instruction Scheduling Utilizing Cache Miss Information
利用高速缓存未命中信息的节能指令调度
  • DOI:
  • 发表时间:
    2006
  • 期刊:
  • 影响因子:
    0
  • 作者:
    Shintaro Kajiwara;Hideki Koike;Kentaro Fukuchi;Kenji Oka;Yoichi Sato;Akihiro Chiyonobu et al.
  • 通讯作者:
    Akihiro Chiyonobu et al.
タイミング違反を許容する省電力加算器における違反検出回路の高速化
加速节能加法器中的违规检测电路,以容忍时序违规
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SATO Toshinori其他文献

Evaluation on Configurable Approximate Circuit for Aging-Induced Timing Violation Tolerance
针对老化引起的时序违规容限的可配置近似电路评估
  • DOI:
  • 发表时间:
    2019
  • 期刊:
  • 影响因子:
    0
  • 作者:
    SATO Toshinori;UKEZONO Tomoaki;Toshinori Sato and Tomoaki Ukezono
  • 通讯作者:
    Toshinori Sato and Tomoaki Ukezono
Tolerating Aging-Induced Timing Violations via Configurable Approximations
通过可配置的近似值容忍老化引起的时序违规
  • DOI:
  • 发表时间:
    2019
  • 期刊:
  • 影响因子:
    0
  • 作者:
    SATO Toshinori;UKEZONO Tomoaki;Toshinori Sato and Tomoaki Ukezono;Toshinori Sato and Tomoaki Ukezono;Toshinori Sato and Tomoaki Ukezono;Toshinori Sato and Tomoaki Ukezono
  • 通讯作者:
    Toshinori Sato and Tomoaki Ukezono
Exploiting Configurable Approximations for Tolerating Aging-induced Timing Violations
利用可配置的近似来容忍老化引起的时序违规
A Dynamically Configurable Approximate Array Multiplier with Exact Mode
具有精确模式的动态可配置近似阵列乘法器
  • DOI:
  • 发表时间:
    2020
  • 期刊:
  • 影响因子:
    0
  • 作者:
    SATO Toshinori;UKEZONO Tomoaki
  • 通讯作者:
    UKEZONO Tomoaki
On Applications of Configurable Approximation to Irregular Voltage
论可配置逼近在不规则电压中的应用
  • DOI:
  • 发表时间:
    2019
  • 期刊:
  • 影响因子:
    0
  • 作者:
    SATO Toshinori;UKEZONO Tomoaki;Toshinori Sato and Tomoaki Ukezono;Toshinori Sato and Tomoaki Ukezono;Toshinori Sato and Tomoaki Ukezono
  • 通讯作者:
    Toshinori Sato and Tomoaki Ukezono

SATO Toshinori的其他文献

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{{ truncateString('SATO Toshinori', 18)}}的其他基金

Study on the Boso slow slip events through observation using ocean bottom pressure gauges and model simulation
房总慢滑移事件的海底压力计观测与模型模拟研究
  • 批准号:
    25287109
  • 财政年份:
    2013
  • 资助金额:
    $ 5.12万
  • 项目类别:
    Grant-in-Aid for Scientific Research (B)
Development of novel drug delivery system using ganglioside-binding peptides
使用神经节苷脂结合肽开发新型药物递送系统
  • 批准号:
    24650283
  • 财政年份:
    2012
  • 资助金额:
    $ 5.12万
  • 项目类别:
    Grant-in-Aid for Challenging Exploratory Research
A Study on Reconstructing Memory Hierarchy that Utilizes Emerging Devices
利用新兴设备重建内存层次结构的研究
  • 批准号:
    23650026
  • 财政年份:
    2011
  • 资助金额:
    $ 5.12万
  • 项目类别:
    Grant-in-Aid for Challenging Exploratory Research
Comparative glycomics toward the analysis of molecular mechanism of tumor metastasis using saccharide primer method.
利用糖引物法分析肿瘤转移的分子机制的比较糖组学。
  • 批准号:
    22651083
  • 财政年份:
    2010
  • 资助金额:
    $ 5.12万
  • 项目类别:
    Grant-in-Aid for Challenging Exploratory Research
Afterslip distribution of large earthquakes with viscoelastic and poroelastic responses
具有粘弹性和孔隙弹性响应的大地震后滑分布
  • 批准号:
    20540404
  • 财政年份:
    2008
  • 资助金额:
    $ 5.12万
  • 项目类别:
    Grant-in-Aid for Scientific Research (C)
A Study on Processor Architectures that are tolerable to Soft-error, Process variation, and Aging.
关于可容忍软错误、过程变化和老化的处理器架构的研究。
  • 批准号:
    20300019
  • 财政年份:
    2008
  • 资助金额:
    $ 5.12万
  • 项目类别:
    Grant-in-Aid for Scientific Research (B)
Development of infection inhibitors using molecular evolutional phage library method
利用分子进化噬菌体库方法开发感染抑制剂
  • 批准号:
    17300159
  • 财政年份:
    2005
  • 资助金额:
    $ 5.12万
  • 项目类别:
    Grant-in-Aid for Scientific Research (B)
The development of inhibitors for the infection using phage library
利用噬菌体库开发感染抑制剂
  • 批准号:
    14380411
  • 财政年份:
    2002
  • 资助金额:
    $ 5.12万
  • 项目类别:
    Grant-in-Aid for Scientific Research (B)
A Study on How Implementing Microprocessors Exploiting Instruction Level Parallelism
关于如何实现微处理器利用指令级并行性的研究
  • 批准号:
    13558030
  • 财政年份:
    2001
  • 资助金额:
    $ 5.12万
  • 项目类别:
    Grant-in-Aid for Scientific Research (B)
Seismic structure inversion of refraction and reflection waves by progressive model development method
渐进模型开发法折射反射波地震结构反演
  • 批准号:
    12640401
  • 财政年份:
    2000
  • 资助金额:
    $ 5.12万
  • 项目类别:
    Grant-in-Aid for Scientific Research (C)

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Microscale enabled advanced flow and heat transfer technologies featuring high performance and low power consumption; Acronym: Micro-FloTec
微尺度实现了高性能、低功耗的先进流动和传热技术;
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    EP/Y004973/1
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I-Corps: Low Power Memory Chips
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FuSe-TG: Ultra-low-power and Robust Autonomy of Edge Robotics with 2D Semiconductors
FuSe-TG:采用 2D 半导体的边缘机器人的超低功耗和鲁棒自主性
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使用实验和计算方法开发低功耗多铁存储器
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ACED Fab:超快、低功耗 AI 芯片,配备新型 MRAM,用于边缘学习和推理
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Micro-FloTec:Microscale 支持先进的流动和传热技术,具有高性能和低功耗的特点
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Development of Low-Power Autonomous Decentralized Scheduling Technology for IoT Environment
物联网环境低功耗自主分散调度技术开发
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    23K13331
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Achieving low-power and high-performance ultra-scalable processors with novel architecture
通过新颖的架构实现低功耗、高性能的超可扩展处理器
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