Research on improving energy efficiency of embedded processors in ubiquitous information devices

功耗是嵌入式微处理器设计中的一个主要问题。降低功耗也是通用微处理器的关键设计目标。由于它们需要高性能和低功耗，因此以性能为代价的功耗降低是不能接受的。有很多设备级技术可以在保持性能的同时降低功耗。他们选择非关键路径作为低功耗设计的候选者，而面向性能的设计仅用于速度关键路径。同样的原理也适用于架构级设计。我们评估的技术，它利用动态信息的指令关键性，以降低功耗。我们评估了一种基于指令关键度的指令引导策略，发现它在降低性能的同时，仍然具有很高的能效。在深亚微米（DSM）半导体技术中，一种被称为“最坏情况设计”的保守方法将不会很快奏效。DSM增加了噪声和工艺变化，并要求降低电源电压，从而降低了最坏情况设计方法所需的设计裕度。设计微处理器时，我们必须考虑典型情况而不是最坏情况。CTV（Constructive Timing Violation）范式就是这样一种设计方法，设计人员专注于典型的情况，而不是担心非常罕见的最坏情况。我们已经设计了两种类型的ALU，利用CTV，其中每一个都有自己的问题，在规模和速度。为了解决这些问题，我们提出利用加法器-比较器作为故障检测电路。使用Verilog-HDL，我们实现了一个进位选择加法器，利用CTV，并评估它的逻辑综合后的逻辑模拟延迟信息。据观察，实现了能源效率的实质性改善。

Power consumption is a major concern in embedded microprocessors design. Reducing power has also been a critical design goal for general-purpose microprocessors. Since they require high performance as well as low power, power reduction at the cost of performance cannot be accepted. There are a lot of device-level techniques that reduce power with maintaining performance. They select non-critical paths as candidates for low-power design, and performance-oriented design is used only in speed-critical paths. The same philosophy can be applied to architectural-level design. We evaluate a technique, which exploits dynamic information regarding instruction criticality in order to reduce power. We evaluate an instruction steering policy for a clustered microarchitecture, which is based on instruction criticality, and find it is substantially energy-efficient while it suffers performance degradation.In the deep submicron (DSM) semiconductor technologies, a conservative approach called "worst-case design" will not work very soon. The DSM increases noise and process variations and requires supply voltage reduction, and thus reduces design margins that worst-case design methodologies require. We have to design microprocessors by considering typical case rather than worst case. The Constructive Timing Violation (CTV) paradigm is such a design methodology, where designers are focusing on typical cases rather than worrying about very rare worst cases. We have designed two types of ALUs that utilize the CTV, each of which has its own problems in size and in speed. In order to solve the problems, we propose to utilize an adder-comparator as the fault detection circuit. Using Verilog-HDL, we implement a carry select adder that utilizes the CTV, and evaluate it on logic simulations after logic synthesis with delay information. It is observed that substaintial improvement in energy efficiency is achieved.