INTEGRATION OF NEURAL NETWORKS USING SUPERCONDUCTIVE DEVICES

使用超导器件集成神经网络

• 批准号: 06555112
• 负责人: NAKAJIMA Koji
• 金额: $ 5.12万
• 依托单位: TOHOKU UNIVERSITY
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for Developmental Scientific Research (B)
• 财政年份: 1994
• 资助国家: 日本
• 起止时间: 1994 至 1995
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-06555112/
• 关键词: Fluxon; Neural Network; Superconductor; Integrated Circuits; Variable Synapses; A; D Converter; Flux Quantum; SQUID; 時速量子

We have designed and fabricated three types of Josephson integrated circuits ; a 3-bit neuron-based A/D converter, an RS flip-flop circuit, and extended phase-mode logic circuits.The 3-bit neuron-based A/D converter comprises three neuron devices and three synapse devices which we have developed recently. The circuit has been integrated using a Nb/ AlOx/Nb junction process and tested with low-frequency analog input. We have presented the experimental operation in Appl. Phys. Lett. and IEEE Trans. Appl. Superconduct.The RS flip-flop, which is designed for a memory device in superconducting neural networks, is composed of two superconducting neuron devices and two fixed synapse resistors. Numerical simulation results show its high speed operation up to 50GHz, which we have presented in IEICE Trans. Electron. Experimental results have been submitted to IEEE Trans. Appl. Superconduct.The extended phase-mode logic (EPL) circuits are designed for control units in superconducting neural networks. The EPL circuits utilizes a single-flux-quantum as an information bit. Test results for an INHIBIT gate, which is one of universal operations in terms of Boolean algebra, has been published in IEEE Trans. Appl. Superconduct. Test results for a binaly counter circuit has been submitted to IEICE Trans. Electron.

我们设计并制作了三种约瑟夫森集成电路：3位神经元A/D转换器、RS触发器电路和扩展相模逻辑电路。3位神经元A/D转换器由我们最近开发的三个神经元器件和三个突触器件组成。该电路已集成使用Nb/ AlOx/Nb结工艺和低频模拟输入测试。我们已经在《应用物理快报》上介绍了实验操作。RS触发器由两个超导神经元器件和两个固定突触电阻组成，是为超导神经网络中的存储器件而设计的。数值模拟结果表明，它的工作频率可达50 GHz，已在IEICE Trans. Electron上发表，实验结果已提交给IEEE Trans. Appl. Superconduct。EPL电路利用单通量量子作为信息比特。作为布尔代数中的一种通用运算，INHIBIT门的测试结果已发表在IEEE Trans. Appl. Superconduct上。二进制计数器电路的测试结果已提交给IEICE电子交易。

项目成果

ONOMI,Takeshi et. al: "Extended Phase-Mode Logic-Circuits with Resistive Ground Contact." IEEE Trans. Appl. Superconduct. vol. 5. 3464-3471 (1995)

小野武等。

Y. Mizugaki et. al: "Neuro-Base Josephson Flip-Flop" IEICE Trans. Electron.E78-C. 531-534 (1995)

Y.水垣等。

NAKAJIMA,Koji et. al: "Hardware Implementation of New Analog Memory for Neural Networks" IEICE Trans. Electron.vol. E78-C. 101-105 (1995)

中岛浩二等。

H.Won: "A Pulsating Neural Network" Extended Abstracts of the 1994 Int.Conf.on SSDM. 379-381 (1994)

H.Won：1994 年 Int.Conf.on SSDM 的“脉动神经网络”扩展摘要。

S. Sato et. al: "LSI Neural Chip of Pulse-Output Network with Programmable Synapse" IEICE Trans. Electron.E78-C. 94-100 (1995)

S.佐藤等。