High speed IC Design with novel dielectrics for 5G infrastructure and precision electronics

集成电路行业中一个无可争议的趋势是制造几何形状的缩放。除了低功耗、高速度和高集成度的明显优势外，这一趋势也给设计人员带来了新的挑战。其中一个权衡是使用低k介电介质的后端（BEOL）电容器。新电介质允许单位面积更高的电容，但代价是增加电介质吸收和随机失配。本计画将深入探讨电容器的非理想性，以限制目前最先进的数值转换器的效能。研究的主要领域集中在电容器失配漂移和介质吸收。在一群世界领先的数据转换器专家和学者的协助下，您将获得电路设计，布局，表征，数据分析和建模方面的经验

One of the undisputed trends in the IC industry is the scaling of the fabrication geometries. Besides the clear benefits of lower power consumption, higher speed and higher integration, this trend present new challenges to designers. One of these trade-offs is the usage of back end of line (BEOL) capacitors with low-k dielectrics. The new dielectric allows a higher capacitance per unit area but comes at the cost of increased dielectric absorption and random mismatch. This project will explore in-depth analysis of the capacitor non- idealities limiting the performance of the state of art numerical converters. The main areas of investigation focus on the capacitor mismatch drift and dielectric absorption. Assisted by a group of world leading data converter specialists and academics, you will gather experience in circuit design, layout, characterisation, data analysis and modelling