Optimising Hardware Acceleration for Financial Computation

优化金融计算的硬件加速

• 批准号: EP/D062322/1
• 负责人: Wayne Luk
• 金额: $ 85.71万
• 依托单位: Imperial College London
• 依托单位国家: 英国
• 项目类别: Research Grant
• 财政年份: 2006
• 资助国家: 英国
• 起止时间: 2006 至 无数据
• 项目状态: 已结题
• 来源: https://gtr.ukri.org/projects?ref=EP%2FD062322%2F1
• 关键词: Optimising; Hardware; Acceleration; Financial; Computation

This proposal describes a three-year research project exploring novel methods and tools for hardware acceleration of financial computation in general, and for Monte Carlo simulation of financial models in particular. Our aim is to exploit the latest software and hardware technologies, particularly those based on advanced reconfigurable hardware such as FPGAs (Field-Programmable Gate Arrays), and to demonstrate the effectiveness of these technologies by applying them to overcome bottlenecks in current and future large-scale financial computation. The technical innovations of this project includes: (1) parameterisation, characterisation and efficient implementation of novel hardware architectures for financial computations; (2) exploitation of the latest software and hardware technologies, such as source-level transformation and advanced reconfigurable gate arrays; (3) techniques for reducing heat dissipation by extensive pipelining, (4) elements for an evolutionary approach to support hardware acceleration for financial analysis, such as adoption of commercial FPGA platforms, facilities to make the technology accessible to finance experts, comparison of standard fixed-point and floating point arithmetic, incremental compilation, and interface to grid technology; (5) elements for a disruptive approach to support hardware acceleration, such as run-time optimisation, coarse-grained devices, non-standard arithmetic, new application opportunities such as real-time risk analysis, and new platform and chip architectures; (6) static and dynamic customisations for adapting architectures to changes in environmental conditions to maintain effective operation, while meeting various constraints such as performance and power consumption; (7) prototype development frameworks for designing and deploying novel architectures supporting financial computations, by combining and specialising our libraries and tools; (8) large-scale applications, based on our experience in financial simulation, to drive the development of architectures and tools for novel computations.

该提案描述了一个为期三年的研究项目，探索新的方法和工具，用于金融计算的硬件加速，特别是金融模型的蒙特卡罗模拟。我们的目标是利用最新的软件和硬件技术，特别是那些基于先进的可重构硬件，如FPGA（现场可编程门阵列），并证明这些技术的有效性，通过应用它们来克服瓶颈，在当前和未来的大规模金融计算。该项目的技术创新包括：（1）金融计算的新型硬件架构的参数化、特征化和高效实现;（2）最新的软件和硬件技术的开发，如源级转换和先进的可重构门阵列;（3）通过大量流水线减少热耗散的技术，（4）用于支持金融分析的硬件加速的进化方法的要素，例如采用商用现场可编程门阵列平台、使金融专家能够使用该技术的设施、标准定点和浮点运算的比较、增量编译以及网格技术的接口;（5）支持硬件加速的破坏性方法的元素，例如运行时优化、粗粒度设备、非标准算法，新的应用机会，如实时风险分析，以及新的平台和芯片架构;（6）静态和动态定制，用于使架构适应环境条件的变化，以保持有效的操作，同时满足各种约束，如性能和功耗;（7）原型开发框架，用于设计和部署支持金融计算的新型架构，通过组合和专门化我们的库和工具;（8）大规模应用，基于我们在金融模拟方面的经验，推动新计算架构和工具的开发。

项目成果

Multivariate Gaussian Random Number Generation Targeting Reconfigurable Hardware

• DOI: 10.1145/1371579.1371584
• 发表时间: 2008-06
• 期刊: ACM Trans. Reconfigurable Technol. Syst.
• 作者: David B. Thomas;W. Luk

Accelerating publish/subscribe matching on reconfigurable supercomputing platform

加速可重构超级计算平台上的发布/订阅匹配

• 发表时间: 2010
• 作者: KH Tsoi

Exploring Reconfigurable Architectures for Tree-Based Option Pricing Models

• DOI: 10.1145/1575779.1575781
• 发表时间: 2009-09
• 期刊: ACM Trans. Reconfigurable Technol. Syst.
• 作者: Qiwei Jin;David B. Thomas;W. Luk;Benjamin Cope