Optimising Hardware Acceleration for Financial Computation

这项提议描述了一个为期三年的研究项目，该项目探索新的方法和工具，以总体上加速金融计算的硬件，特别是用于金融模型的蒙特卡洛模拟。我们的目标是利用最新的软件和硬件技术，特别是那些基于先进的可重新配置硬件的技术，如现场可编程门阵列(现场可编程门阵列)，并通过应用这些技术来克服当前和未来大规模金融计算的瓶颈来展示这些技术的有效性。该项目的技术创新包括：(1)金融计算新的硬件架构的参数化、特征化和高效实现；(2)最新软硬件技术的开发，如源代码级转换和先进的可重构门阵列；(3)通过广泛的流水线减少散热的技术；(4)支持金融分析硬件加速的进化方法的要素，如采用商用FPGA平台、使金融专家能够访问该技术的设施、标准定点和浮点算法的比较、增量编译以及与网格技术的接口；(5)支持硬件加速的颠覆性方法的要素，例如运行时优化、粗粒度设备、非标准算法、实时风险分析等新的应用机会以及新的平台和芯片架构；(6)用于使架构适应环境条件变化以保持有效运行的静态和动态定制，同时满足诸如性能和功耗等各种约束；(7)通过组合和专门化我们的库和工具，用于设计和部署支持金融计算的新型架构的原型开发框架；(8)基于我们在金融模拟方面的经验的大规模应用程序，以推动用于新计算的体系结构和工具的开发。

This proposal describes a three-year research project exploring novel methods and tools for hardware acceleration of financial computation in general, and for Monte Carlo simulation of financial models in particular. Our aim is to exploit the latest software and hardware technologies, particularly those based on advanced reconfigurable hardware such as FPGAs (Field-Programmable Gate Arrays), and to demonstrate the effectiveness of these technologies by applying them to overcome bottlenecks in current and future large-scale financial computation. The technical innovations of this project includes: (1) parameterisation, characterisation and efficient implementation of novel hardware architectures for financial computations; (2) exploitation of the latest software and hardware technologies, such as source-level transformation and advanced reconfigurable gate arrays; (3) techniques for reducing heat dissipation by extensive pipelining, (4) elements for an evolutionary approach to support hardware acceleration for financial analysis, such as adoption of commercial FPGA platforms, facilities to make the technology accessible to finance experts, comparison of standard fixed-point and floating point arithmetic, incremental compilation, and interface to grid technology; (5) elements for a disruptive approach to support hardware acceleration, such as run-time optimisation, coarse-grained devices, non-standard arithmetic, new application opportunities such as real-time risk analysis, and new platform and chip architectures; (6) static and dynamic customisations for adapting architectures to changes in environmental conditions to maintain effective operation, while meeting various constraints such as performance and power consumption; (7) prototype development frameworks for designing and deploying novel architectures supporting financial computations, by combining and specialising our libraries and tools; (8) large-scale applications, based on our experience in financial simulation, to drive the development of architectures and tools for novel computations.