Reconfigurable Architectures for Floating Point Applications
Reconfigurable Architectures for Floating Point Applications
批准号:
EP/D060567/1
负责人:
Wayne Luk
金额:
$62.52万
依托单位:
依托单位国家:
英国
项目类别:
Research Grant
财政年份:
2006
资助国家:
英国
项目状态:
已结题
起止时间:
2006 至 --
中文摘要
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英文摘要
Field programmable gate arrays (FPGAs) are integrated circuits whose functionality can be described via a downloadable bitstream. By downloading different bitstream configurations, customised applications can be developed with improvements in power and area over microprocessor based designs. To date, most FPGA-based applications have used fixed point arithmetic as floating point is expensive to implement on an FPGA. The two leading FPGA vendors, Xilinx and Altera, employ the so called island style architecture in which relatively small logic cells that implement the user-defined logic are surrounded by programmable routing channels.In this project we propose to develop FPGAs that are specifically optimised for floating point applications in signal processing, embedded systems and high performance computing. These will have speed and power advantages over existing FPGAs and microprocessors for floating point intensive computations and, to the best of our knowledge, no previous FPFPGAs have been reported.Three key tools will be developed in the course of this project: the development of a place and route tool that supports generalised FPFPGA architectures; benchmark problems that will be used to measure the performance of proposed FPFPGA archiectures and a tool which will produce integrated circuit layouts from the high level architectural description of the FPFPGA.Our development of the place and route tool will begin from the existing VPR tool developed at the University of Toronto. This will be modified to allow additional integer functional units and floating point units to be added to the basic island style architecture supported by VPR.
期刊论文(3)
专著(0)
科研奖励(0)
会议论文
The Coarse-Grained/Fine-Grained Logic Interface in FPGAs with Embedded Floating-Point Arithmetic Units
具有嵌入式浮点运算单元的 FPGA 中的粗粒度/细粒度逻辑接口
DOI:
10.1155/2008/736203
发表时间:
2008
期刊:
International Journal of Reconfigurable Computing
影响因子:
4.3
作者:
[Yu C]
通讯作者:
Yu C
A Synthesizable Datapath-Oriented Embedded FPGA Fabric for Silicon Debug Applications
适用于芯片调试应用的可综合数据路径嵌入式 FPGA 架构
DOI:
10.1145/1331897.1331903
发表时间:
2008
期刊:
ACM Transactions on Reconfigurable Technology and Systems
影响因子:
2.3
作者:
[Wilton S]
通讯作者:
Wilton S
DART: Design Accelerators by Regulating Transformations
-
批准号:EP/V028251/1
-
项目类别:Research Grant
-
资助金额:$78.22万
-
财政年份:2021
-
负责人:Wayne Luk
-
依托单位:
Application Customisation: Enhancing Design Quality and Developer Productivity
-
批准号:EP/P010040/1
-
项目类别:Research Grant
-
资助金额:$160.98万
-
财政年份:2017
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负责人:Wayne Luk
-
依托单位:
Custom Computing for Advanced Digital Systems
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批准号:EP/I012036/1
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项目类别:Research Grant
-
资助金额:$161.49万
-
财政年份:2010
-
负责人:Wayne Luk
-
依托单位:
Optimising Hardware Acceleration for Financial Computation
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批准号:EP/D062322/1
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项目类别:Research Grant
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资助金额:$85.71万
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财政年份:2006
-
负责人:Wayne Luk
-
依托单位:
海外基金