DART: Design Accelerators by Regulating Transformations

DART：通过调节转换来设计加速器

• 批准号: EP/V028251/1
• 负责人: Wayne Luk
• 金额: $ 78.22万
• 依托单位: Imperial College London
• 依托单位国家: 英国
• 项目类别: Research Grant
• 财政年份: 2021
• 资助国家: 英国
• 起止时间: 2021 至 无数据
• 项目状态: 未结题
• 来源: https://gtr.ukri.org/projects?ref=EP%2FV028251%2F1
• 关键词: DART; Design; Accelerators; Regulating; Transformations

The DART project aims to pioneer a ground-breaking capability to enhance the performance and energy efficiency of reconfigurable hardware accelerators for next-generation computing systems. This capability will be achieved by a novel foundation for a transformation engine based on heterogeneous graphs for design optimisation and diagnosis. While hardware designers are familiar with transformations by Boolean algebra, the proposed research promotes a design-by-transformation style by providing, for the first time, tools which facilitate experimentation with design transformations and their regulation by meta-programming. These tools will cover design space exploration based on machine learning, and end-to-end tool chains mapping designs captured in multiple source languages to heterogeneous reconfigurable devices targeting cloud computing, Internet-of-Things and supercomputing. The proposed approach will be evaluated through a variety of benchmarks involving hardware acceleration, and through codifying strategies for automating the search of neural architectures for hardware implementation with both high accuracy and high efficiency.

DART项目旨在开拓突破性的能力，以提高下一代计算系统的可重构硬件加速器的性能和能源效率。这种能力将通过基于异构图的转换引擎的新基础来实现，用于设计优化和诊断。虽然硬件设计人员熟悉布尔代数的转换，但提出的研究通过首次提供工具来促进设计转换的实验和通过元编程对其进行调节，从而促进了一种按转换设计的风格。这些工具将涵盖基于机器学习的设计空间探索，以及将以多种源语言捕获的设计映射到针对云计算、物联网和超级计算的异构可重构设备的端到端工具链。所提出的方法将通过涉及硬件加速的各种基准测试进行评估，并通过编写策略来自动化搜索神经架构，以实现高精度和高效率的硬件实现。

项目成果

Enabling fast uncertainty estimation

实现快速不确定性估计

• DOI: 10.1145/3489517.3530451
• 发表时间: 2022
• 作者: Fan H

When Monte-Carlo Dropout Meets Multi-Exit: Optimizing Bayesian Neural Networks on FPGA

当蒙特卡罗 Dropout 遇到多出口：在 FPGA 上优化贝叶斯神经网络

• DOI: 10.1109/dac56929.2023.10247954
• 发表时间: 2023
• 作者: Fan H

Optimizing quantum circuit placement via machine learning

通过机器学习优化量子电路布局

• DOI: 10.1145/3489517.3530403
• 发表时间: 2022
• 作者: Fan H

Accelerating Bayesian Neural Networks via Algorithmic and Hardware Optimizations

• DOI: 10.1109/tpds.2022.3153682
• 发表时间: 2022
• 期刊: IEEE Transactions on Parallel and Distributed Systems
• 影响因子: 5.3
• 作者: Hongxiang Fan;Martin Ferianc;Zhiqiang Que;Xinyu Niu;Miguel L. Rodrigues;Wayne Luk

Adaptable Butterfly Accelerator for Attention-based NNs via Hardware and Algorithm Co-design

• DOI: 10.1109/micro56248.2022.00050
• 发表时间: 2022-09
• 期刊: 2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO)
• 作者: Hongxiang Fan;Thomas C. P. Chau;Stylianos I. Venieris;Royson Lee;Alexandros Kouris;W. Luk;N. Lane;M. Abdelfattah