Software-Specified Hardware Acceleration for Energy-Efficient Computing

用于节能计算的软件指定硬件加速

• 批准号: RGPIN-2019-05785
• 负责人: Anderson, Jason
• 金额: $ 4.01万
• 依托单位: University of Toronto
• 依托单位国家: 加拿大
• 项目类别: Discovery Grants Program - Individual
• 财政年份: 2022
• 资助国家: 加拿大
• 起止时间: 2022-01-01 至 2023-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=751558
• 关键词: Software; Specified; Hardware; Acceleration; Energy

Whether it be Uber ride-sharing, social media, or Netflix video streaming, data centre (cloud) computing is the "workhorse" behind countless applications we depend on in today's digital connected society. Data centres represent about 3% of the world's total energy consumption, however, a recent study predicted that they may account for an astounding ~7% of the world's electricity consumed by 2030. The majority of computational work in data centres is done by standard microprocessors. While such processors benefit from logic density increases afforded by Moore's Law, energy efficiency has not improved at the same rate. A proven approach to raise energy efficiency is to customize the computing hardware to the computing task, eliminating the overheads incurred by a generic microprocessor, such as fetching/decoding instructions. Field-programmable gate arrays (FPGAs) are programmable chips that can be configured to realize any digital circuit. FPGAs are thus an ideal media on which to implement custom compute accelerators in data centres, and have been shown to produce orders-of-magnitude improvements in energy efficiency. Major cloud-computing providers have recently announced the deployment of FPGAs in their data centres -- a "game changer" for what was once seen as a niche technology. FPGAs are now a part of the sharing economy: from anywhere in the world, one can rent a cloud FPGA for accelerated energy-efficient custom computing.    FPGAs are poised for a prominent role in energy-efficient data centre computing, however, a challenge is that they are difficult to use by software engineers for two primary reasons: 1) implementing a circuit on an FPGA has historically required knowledge of hardware design, where the circuit is described at a low level of abstraction in a hardware description language, such as VHDL or Verilog, and 2) compiling a design for an FPGA is time intensive, taking up to hours or days, preventing the real-time design -> debug -> execute iterative cycle that software engineers are accustomed to. What is needed is for FPGAs to be software programmable, with the desired behaviour specified at a high level of abstraction, and new approaches and architectures that permit such specifications to be rapidly compiled into the underlying FPGA hardware.    A first thrust undertaken to address the FPGA usability challenge is the application of machine learning techniques within high-level synthesis (HLS). HLS is the automated synthesis of a hardware circuit from a software program. Presently, the quality of circuit (power, performance, area) produced by HLS tools is inferior to human-expert designed hardware. HLS tools are by nature heuristic approaches, and we propose to apply machine learning algorithms, within HLS itself, to raise circuit quality. A second research thrust concerns the architecture of the target FPGA. We propose to attack today's lengthy compile times through compile-time-friendly architectural changes.

无论是Uber拼车、社交媒体还是Netflix视频流，数据中心（云）计算都是我们在当今数字互联社会中所依赖的无数应用程序背后的“主力”。数据中心约占世界总能源消耗的3%，然而，最近的一项研究预测，到2030年，它们可能占世界电力消耗的7%。数据中心的大部分计算工作是由标准微处理器完成的。虽然这样的处理器受益于由摩尔定律提供的逻辑密度增加，但是能量效率没有以相同的速率提高。一种行之有效的提高能源效率的方法是为计算任务定制计算硬件，消除由通用微处理器引起的开销，例如获取/解码指令。现场可编程门阵列（FPGA）是可编程芯片，可以配置为实现任何数字电路。因此，FPGA是在数据中心实现定制计算加速器的理想介质，并且已被证明可以在能源效率方面产生数量级的改进。主要的云计算提供商最近宣布在其数据中心部署FPGA-这是曾经被视为利基技术的“游戏规则改变者”。FPGA现在是共享经济的一部分：从世界任何地方，人们都可以租用云FPGA来加速节能定制计算。 FPGA在高能效数据中心计算中将发挥重要作用，但面临的挑战是，软件工程师很难使用FPGA，主要原因有两个：1）在FPGA上实现电路在历史上需要硬件设计的知识，其中电路以诸如VHDL或Verilog的硬件描述语言在低抽象级别上描述，以及2）编译FPGA的设计是时间密集的，花费数小时或数天，妨碍了软件工程师所习惯的实时设计->调试->执行迭代循环。需要的是FPGA是软件可编程的，具有在高抽象级别指定的期望行为，以及允许将这种规范快速编译到底层FPGA硬件中的新方法和架构。 解决FPGA可用性挑战的第一个推动力是在高级综合（HLS）中应用机器学习技术。HLS是从软件程序自动合成硬件电路。目前，HLS工具产生的电路质量（功率，性能，面积）不如人类专家设计的硬件。HLS工具本质上是启发式方法，我们建议在HLS本身中应用机器学习算法来提高电路质量。第二个研究重点涉及目标FPGA的架构。我们建议通过编译时友好的架构变化来攻击今天冗长的编译时间。