Device Electronics Based on nanoWires and NanoTubes

有相当大的范围CNFET和硅纳米线与他们的弹道传输能力，被引入到标准的CMOS通过混合technology.The主要原因，目前阻碍使用这种技术是一个可控的制造技术在MOS型配置与可预测的设备特性的情况下。适当的物理模型和模拟工具是解决这一问题所必需的。合作研究涉及四个伙伴：1）比萨：有触点的门控结构中弹道输运的原子模型。(2)维也纳：包括散射在内的有效质量输运方法。(3)德蒙福特大学：剑桥制造的器件的特性、参数提取和缺陷分析。这些参数将输入比萨和维也纳的模型。(4)剑桥大学：该项目的总体目标是进行理论与实验相结合的综合分析，以便为未来此类技术的制造提供一些基本的设计规则。

There is considerable scope for CNFETs and Si Nanowires with their capability of ballistic transport, to be introduced into standard CMOS via a hybrid technology.The main reason currently hampering the use of this technology is an absence of controlled fabrication techniques in MOS type configurations with predictable device characteristics. Adequate physical models and simulation tools are necessary to address this issue.collaborative research involves four partners: 1) Pisa : Atomistic modelling of ballistic transport in gated structures with contacts. (2) Vienna: Effective mass approach to transport inclusive of scattering.(3) De Montfort University : Characterisation, parameter extraction and defect analysis of devices fabricated at Cambridge. The parameters will be fed into the modelling at Pisa and Vienna.(4) Cambridge University : Fabrication of devices.overall goal of the project is to carry out a comprehensive analysis linking theory with experiment to enable some fundamental design rules for fabrication of such technologies in future.